Megafunction

scfifo (Single-Clock FIFO) Megafunction



Parameterized single-clock FIFO megafunction. The scfifo function uses mega RAMs or M4K or M512 memory blocks in Stratix and Stratix GX devices, M4K memory blocks in Cyclone devices, Embedded System Blocks (ESB) in APEX 20K, APEX II, ARM®-based Excalibur, and Mercury devices, Embedded Array Blocks (EAB) in ACEX® 1K and FLEX 10KE devices, or DFFE primitives or latch arrays in FLEX® 6000, MAX® 3000, and MAX 7000 devices or if the USE_EAB parameter is set to "OFF". Altera® strongly recommends using synchronous rather than asynchronous RAM functions.

NOTE The Quartus® II Compiler automatically implements suitable portions of this function in mega RAMs or M4K or M512 memory blocks in Stratix and Stratix GX devices, in M4K memory blocks in Cyclone devices, in ESBs in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, and in EABs in ACEX 1K and FLEX 10KE devices. The Compiler automatically implements this function in logic cells in FLEX 6000, MAX 3000, and MAX 7000 devices.

Altera also recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

NOTE The scfifo function must contain at least one word before it is able to read a word and must have at least one unused word before it is able to write a word.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION scfifo (data[(LPM_WIDTH)-1..0], wrreq, rdreq, clock, aclr,
      sclr)
   WITH (LPM_WIDTH, LPM_NUMWORDS, LPM_SHOWAHEAD,
      UNDERFLOW_CHECKING, OVERFLOW_CHECKING, ALMOST_FULL_VALUE,
      ALMOST_EMPTY_VALUE, ALLOW_RWCYCLE_WHEN_FULL, USE_EAB,
      MAXIMIZE_SPEED)
   RETURNS (q[(LPM_WIDTH)-1..0], empty, full, almost_full,
      almost_empty,
      usedw[(LPM_NUMWORDS>=2 ? CEIL(LOG2(LPM_NUMWORDS)):1)-1..0]

 

VHDL Component Declaration:

COMPONENT scfifo
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_WIDTHU: POSITIVE;
      LPM_NUMWORDS: POSITIVE;
      LPM_SHOWAHEAD: STRING := "OFF";
      ALMOST_FULL_VALUE: POSITIVE:= 0;
      ALMOST_EMPTY_VALUE: POSITIVE:= 0;
      ALLOW_RWCYCLE_WHEN_FULL: STRING := "OFF";
      MAXIMIZE_SPEED: POSITIVE:= 5;
      OVERFLOW_CHECKING: STRING:= "ON";
      UNDERFLOW_CHECKING: STRING:= "ON");
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      clock, wrreq, rdreq, aclr, sclr: IN STD_LOGIC;
      full, empty, almost_full, almost_empty: OUT STD_LOGIC;
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
      usedw: OUT STD_LOGIC_VECTOR(LPM_WIDTHU-1 DOWNTO 0));
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

LIBRARY altera_mf
USE altera_mf.altera_mf_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
data[] Yes Data input to the scfifo. Input port LPM_WIDTH wide.
clock Yes Positive-edge-triggered clock.  
wrreq Yes Write request. The data[] port is written to the scfifo. Writing is disabled if full = 1.
rdreq Yes Read request. The oldest data in the scfifo goes to the q[] port. Reading is disabled if empty = 1.
aclr No Resets the scfifo to empty. The output data is not affected by the data in the aclr port.
sclr No Resets the scfifo to empty.  

OUTPUT PORTS

Port Name Required Description Comments
q[] Yes Data output from the scfifo. Output port LPM_WIDTH wide.
full No Indicates that the scfifo is full and disables the wrreq port. Asserted when usedw[] = LPM_NUMWORDS.
empty No Indicates that the scfifo is empty and disables the rdreq port. Asserted when usedw[] = 0.
almost_full No Indicates that the scfifo is almost full. Asserted when usedw[] >= ALMOST_FULL_VALUE.
almost_empty No Indicates that the scfifo is almost empty. Asserted when usedw[] < ALMOST_EMPTY_VALUE.
usedw[] No The number of words that are currently in the scfifo. Output port with width [CEIL(LOG2(LPM_NUMWORDS))-1..0]. If the value of LPM_NUMWORDS is a power of 2, you can use the full output as an extra bit and append it to usedw[]. Example

 

Parameter Descriptions:

Parameter Type Required Description
LPM_WIDTH Integer Yes Width of data[] and q[] ports.
LPM_NUMWORDS Integer Yes Depth of the scfifo. Number of words stored in memory, which is usually a power of 2.
LPM_WIDTHU Integer Yes (VHDL only) Width of usedw[] port.
ALMOST_FULL_VALUE Integer No The threshold value for the almost_full port.
ALMOST_EMPTY_VALUE Integer No The threshold value for the almost_empty port.
LPM_SHOWAHEAD String No Allows the data to appear on q[] before rdreq is asserted when set to "ON". Values are "ON" or "OFF" (the default is "OFF").
ALLOW_RWCYCLE_WHEN_FULL String No Allows combined read/write cycles to an already full scfifo, so that it remains full. Values are "ON" or "OFF" (the default is "OFF"). This parameter is used only when the OVERFLOW_CHECKING parameter is set to "ON".
USE_EAB String No Altera-specific parameter. Values are "ON", "OFF", and "UNUSED". Setting the USE_EAB parameter to "OFF" prevents the Quartus II software from using ESBs to implement the logic in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, or EABs in ACEX 1K and FLEX 10KE devices; it can use only flipflops or latches. (The "ON" setting is not useful in memory functions: the Quartus II software automatically implements memory functions in ESBs or EABs by default.) This parameter is not available for simulation with other EDA simulators and for FLEX 6000, MAX 3000, MAX 7000, Stratix, and Stratix GX devices.
MAXIMIZE_SPEED Integer No Altera-specific parameter. You can specify a value between 0 and 10. If used, the Quartus II software attempts to optimize a specific instance of the scfifo function for speed rather than area, and overrides the setting of the Optimization Technique option in the Assignment Organizer dialog box (Assignment menu). If MAXIMIZE_SPEED is unused, the value of the Optimization Technique option is used instead. If the setting for MAXIMIZE_SPEED is 6 or higher, the Compiler will optimize scfifo megafunctions for higher speed; if the setting is 5 or less, the Compiler will optimize for smaller area.
OVERFLOW_CHECKING String No Disables the overflow-checking logic when set to "OFF", so that full is no longer checked for wrreq. Values are "ON" or "OFF" (the default is "ON").
NOTE Writing to a full scfifo gives unpredictable results.
UNDERFLOW_CHECKING String No Disables the underflow-checking logic when set to "OFF", so that empty is no longer checked for rdreq. Values are "ON" or "OFF" (the default is "ON").
Reading an empty scfifo gives unpredictable results.

 

Truth Table/Functionality:

The scfifo function represents memory with synchronous inputs and/or outputs.

Synchronous Memory Operations
aclr sclr Clock rdreq wrreq Function
L L X L L No change.
L L notRising Edge X X No change (requires positive clock edge).
L L Rising Edge L H Write data to memory.
L L Rising Edge H L Read memory and update q[].
L L Rising Edge H H Write data to memory and read memory to q[].
H L X X X Resets the scfifo to empty. The q[] port becomes undefined.
L H Rising Edge X X Resets the scfifo to empty. The q[] port becomes undefined.

 

Resource Usage:

The following table summarizes the resource usage for an scfifo megafunction used to implement an 8-bit-wide FIFO buffer. A depth of 8 words is used for the FLEX 6000, MAX 3000, and MAX 7000 device families. A depth of 256 words is used for all other device families.

Design Goals Design Results
Device Family
APEX 20K
Width Depth Logic Cells ESBs
8 256 221 2

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