A logic option that specifies the overall goal for logic optimization, that is, whether to attempt to achieve maximum speed performance or minimum area usage during compilation.
You can select one of the following settings:
| Area | The Compiler makes the design as small as possible in order to minimize resource usage. |
| Speed | The Compiler chooses a design implementation that has the fastest fmax. |
This option is ignored if it is assigned to anything other than a design entity. This option is available for all Altera® devices supported by the Quartus® II software.
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- PLDWorld - |
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