csdpram Megafunction

csdpram (Cycle-Shared Dual-Port RAM) Megafunction

Parameterized cycle-shared dual-port RAM megafunction. Altera^® recommends using lpm_ram_dp for dual-port RAM functions in ACEX^® 1K, APEX^™ 20K, APEX^™ II, ARM^®-based Excalibur^™, FLEX 10KE, and Mercury^™ projects. The csdpram function uses Embedded System Blocks (ESB) in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, Embedded Array Blocks (EAB) in ACEX 1K and FLEX 10KE devices, or DFFE primitives or latch arrays in FLEX^® 6000, MAX^® 3000, and MAX 7000 devices or if the USE_EAB parameter is set to "OFF". Altera strongly recommends using synchronous rather than asynchronous RAM functions. The csdpram megafunction is provided for backward compatibility only, and is not available for Cyclone^™, Stratix^™, and Stratix^™ GX designs.

The Quartus^® II Compiler automatically implements suitable portions of this function in ESBs in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, and in EABs in ACEX 1K and FLEX 10KE devices. The Compiler automatically implements this function in logic cells in FLEX 6000, MAX 3000, and MAX 7000 devices.The csdpram function is not available for VHDL designs.

This topic contains the following information:

AHDL Function Prototype (also applies to Verilog HDL)
VHDL Component Declaration
VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
Port Descriptions
Parameter Descriptions

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION csdpram (dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0],
      addressa[LPM_WIDTHAD-1..0], addressb[LPM_WIDTHAD-1..0], wea,
      web, clock, clockx2)
   WITH (LPM_WIDTH, LPM_WIDTHAD, LPM_NUMWORDS, FILE)
   RETURNS (qa[LPM_WIDTH-1..0], qb[LPM_WIDTH-1..0], busy);

VHDL Component Declaration:

COMPONENT csdpram
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_WIDTHAD: POSITIVE;
      LPM_NUMWORDS: POSITIVE;
      FILE: STRING := "UNUSED");
   PORT (dataa, datab: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      addressa, addressb: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO
      0);
      clock, clockx2, wea, web: IN STD_LOGIC;
      qa, qb: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      busy: OUT STD_LOGIC);
END COMPONENT;

VHDL LIBRARY-USE Declaration

LIBRARY lpm;
USE lpm.lpm_components.all;

Port Descriptions:

INPUT PORTS

Port Name	Required	Description	Comments
`dataa[]`	Yes	Data input to the memory.	Input port `LPM_WIDTH` wide.
`datab[]`	Yes	Data input to the memory.	Input port `LPM_WIDTH` wide.
`addressa[]`	Yes	Address input to the memory.
`addressb[]`	Yes	Address input to the memory.
`wea`	Yes	Write Enable input.
`web`	Yes	Write Enable input.
`clock`	Yes	Positive-edge-triggered clock.
`clockx2`	Yes	Positive-edge-triggered clock operating at twice the frequency of `clock`.

OUTPUT PORTS

Port Name	Required	Description	Comments
`qa[]`	Yes	Data output from the memory.	Output port `LPM_WIDTH` wide. The `qa[]` and `qb[]` outputs are valid before and during the next rising edge of clock but may not be valid at other times.
`qb[]`	Yes	Data output from the memory.	Output port `LPM_WIDTH` wide. The `qa[]` and `qb[]` outputs are valid before and during the next rising edge of clock but may not be valid at other times.
`busy`	No	Indicates that `addressa = addressb` and that `dataa` is writing data.

Parameter Descriptions:

Parameter	Type	Required	Description
`LPM_WIDTH`	Integer	Yes	Width of `data[]`, `datab[]`, `qa[]`, and `qb[]` ports.
`LPM_WIDTHAD`	Integer	Yes	Width of the `addressa[]` and `addressb[]` ports. `LPM_WIDTHAD` should be (but is not required to be) equal to `LOG2(LPM_NUMWORDS)`. If `LPM_WIDTHAD` is too small, some memory locations will not be addressable. If it is too large, the addresses that are too high will return undefined (X) logic levels.
`LPM_NUMWORDS`	Integer	No	Number of words stored in memory. In general, this value should be (but is not required to be) 2 ^ `LPM_WIDTHAD-`1 < `LPM_NUMWORDS` <= 2 ^ `LPM_WIDTHAD`. If omitted, the default is 2 ^ `LPM_WIDTHAD`.
`FILE`	String	No	Name of the Memory Initialization File (.mif) or Hexadecimal (Intel-Format) Output File (.hexout) containing RAM initialization data (`"`<file name>`"`), or `"UNUSED"`. If omitted, contents default to all 0s. The `wea` and `web` port must be registered to support memory initialization.
`USE_EAB`	String	No	Altera-specific parameter. Values are `"ON"`, `"OFF"`, and `"UNUSED"`. Setting the `USE_EAB` parameter to `"OFF"` prevents the Quartus II software from using ESBs to implement the logic in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, or EABs in ACEX 1K and FLEX 10KE devices; it can only use flipflops or latches. (The `"ON"` setting is not useful in memory functions: the Quartus II software automatically implements memory functions in ESBs or EABs by default.) This parameter is not available for simulation with other EDA simulators and for FLEX 6000, MAX 3000, and MAX 7000 devices.

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