See Also

Parameterized triple-port RAM megafunction. This megafunction is provided only for backward compatibility in Cyclone^™, Stratix^™, and Stratix^™ GX designs; instead, Altera^® recommends using the altsyncram megafunction.

The Quartus® II Compiler automatically implements suitable portions of this function in Embedded System Blocks (ESBs) in APEX™ 20K, APEX™ II, ARM®-based Excalibur™, and Mercury™ devices, and in Embedded Array Blocks (EAB) in ACEX® 1K and FLEX 10KE devices. The Compiler automatically implements this function in logic cells in FLEX® 6000, MAX® 3000, and MAX 7000 devices.

Altera recommends instantiating this function as described in Using the MegaWizard^® Plug-In Manager.

This topic contains the following information:

• AHDL Function Prototype (also applies to Verilog HDL)
• VHDL Component Declaration
• VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
• Port Descriptions
• Parameter Descriptions
• Truth Table/Functionality
• Resource Usage

FUNCTION alt3pram (data[WIDTH-1..0], rdaddress_a[WIDTHAD-1..0],
      rdaddress_b[WIDTHAD-1..0], wraddress[WIDTHAD-1..0], wren,
      inclock, inclocken, rden_a, rden_b, outclock, outclocken, aclr)
   WITH (WIDTH, WIDTHAD, NUMWORDS, LPM_FILE, INDATA_REG, INDATA_ACLR,
      WRITE_REG, WRITE_ACLR, RDADDRESS_REG_A, RDADDRESS_REG_B, 
      RDADDRESS_ACLR_A, RDADDRESS_ACLR_B, RDCONTROL_REG_A, RDCONTROL_REG_B,
      RDCONTROL_ACLR_A, RDCONTROL_ACLR_B, OUTDATA_REG_A, OUTDATA_REG_B,
      OUTDATA_ACLR_A, OUTDATA_ACLR_B, USE_EAB)
   RETURNS (qa[WIDTH-1..0], qb[WIDTH-1..0]);

COMPONENT alt3pram
   GENERIC ( WIDTH: NATURAL;
      WIDTHAD          : NATURAL;
      NUMWORDS         : NATURAL;
      LPM_FILE         : STRING := "UNUSED";
      LPM_HINT         : STRING := "USE_EAB=ON";
      INDATA_REG       : STRING := "UNREGISTERED";
      INDATA_ACLR      : STRING := "OFF";
      WRITE_REG        : STRING := "UNREGISTERED";
      WRITE_ACLR       : STRING := "OFF";
      RDADDRESS_REG_A  : STRING := "UNREGISTERED";
      RDADDRESS_ACLR_A : STRING := "OFF";
      RDADDRESS_REG_B  : STRING := "UNREGISTERED";
      RDADDRESS_ACLR_B : STRING := "OFF";		
      RDCONTROL_REG_A  : STRING := "UNREGISTERED";
      RDCONTROL_ACLR_A : STRING := "OFF";
      RDCONTROL_REG_B  : STRING := "UNREGISTERED";
      RDCONTROL_ACLR_B : STRING := "OFF";		
      OUTDATA_REG_A    : STRING := "UNREGISTERED";
      OUTDATA_ACLR_A   : STRING := "OFF"
      OUTDATA_REG_B    : STRING := "UNREGISTERED";
      OUTDATA_ACLR_B   : STRING := "OFF");

    PORT (wren, inclock, outclock, aclr: IN STD_LOGIC := '0';
        data: IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
        wraddress, rdaddress_a, rdaddress_b: IN STD_LOGIC_VECTOR(WIDTHAD-1 DOWNTO 0);
        inclocken, rden_a, rden_b, outclocken: IN STD_LOGIC := '1';
        q_a, q_b: OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) );
END COMPONENT;

LIBRARY altera_mf
USE altera_mf.altera_mf_components.all;

INPUT PORTS

OUTPUT PORTS

The alt3pram function represents asynchronous memory or memory with synchronous inputs and/or outputs.

Synchronous Write to Memory (all inputs registered)
inclock inclocken wren Function   X L L No change. not H H No change. L X No change. H H The memory location pointed to by wraddress[] is loaded with data[].

Synchronous Read from Memory
inclock inclocken rden_a/rden_b Function  X L L No change. not H H No change. L X No change. H H The q_a[]/q_b[]port outputs the contents of the memory location.

Totally asynchronous memory operations occur when neither inclock nor outclock is connected.

Uses one embedded cell per data output bit for ACEX 1K, APEX 20K, APEX II, ARM-based Excalibur, FLEX 10KE, and Mercury devices; however, in FLEX 6000, MAX 3000, and MAX 7000 devices, or if the USE_EAB paramter is set to "OFF", uses one logic cell per memory bit.

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