Overviews

Commands

See Also

To simulate embedded processor bus transactions:

1. Generate the uPCore Transaction Model Input File (.mbus_in) that describes the embedded processor bus transactions over the Stripe-to-PLD Bridge via the Stripe Master-Port.

2. Create the uPCore Transaction Model Slave Configuration File (cfg.sbus_in) that configures the memory spaces in the stripe for simulating embedded processor bus transactions.

3. Create the uPCore Transaction Model Slave Input Files (.sbus_in) that specify the initial contents of the memory spaces in the Excalibur^™ embedded processor stripe.

4. Specify the uPCore Transaction Model Input File as one of the Simulator options.

5. Perform a functional or timing simulation.

6. If you want to view output bus transactions, open the uPCore Transaction Model Output File (.mbus_out) and uPCore Transaction Model Slave Output File (.sbus_out) that were generated during simulation.