See Also

Parameterized multipy-accumulate megafunction. The altmult_accum megafunction consists of a single multiplier feeding an accumulator.

This topic contains the following information:

• AHDL Function Prototype (also applies to Verilog HDL)
• VHDL Component Declaration
• VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
• Port Descriptions
• Parameter Descriptions

FUNCTION altmult_accum (dataa[NUMBER_OF_MULTIPLIERS * WIDTH_A - 1..0], datab[NUMBER_OF_MULTIPLIERS * WIDTH_B - 1..0], addnsub, accum_sload,
      signa, signb, clock0, clock1, clock2, clock3, ena0, ena1, ena2, ena3, aclr0, aclr1,
      aclr2, aclr3 ) 
   WITH (WIDTH_A, WIDTH_B, WIDTH_RESULT, INPUT_REG_A, INPUT_ACLR_A, INPUT_REG_B, INPUT_ACLR_B,
      ADDNSUB_REG, ADDNSUB_ACLR, ADDNSUB_PIPELINE_REG, ADDNSUB_PIPELINE_ACLR, ACCUM_DIRECTION, 
      ACCUM_SLOAD_REG, ACCUM_SLOAD_ACLR, ACCUM_SLOAD_PIPELINE_REG, ACCUM_SLOAD_PIPELINE_ACLR, 
      REPRESENTATION_A, SIGN_REG_A, SIGN_ACLR_A, SIGN_PIPELINE_REG_A, SIGN_PIPELINE_ACLR_A, 
      SIGN_REG_B, SIGN_ACLR_B, REPRESENTATION_B, SIGN_PIPELINE_REG_B, SIGN_PIPELINE_ACLR_B, 
      MULTIPLIER_REG, MULTIPLIER_ACLR, OUTPUT_REG, OUTPUT_ACLR, EXTRA_LATENCY, 
      DEDICATED_MULTIPLIER_CIRCUITRY ) 
   RETURNS  (result[WIDTH_RESULT - 1..0], overflow, scanouta[WIDTH_A - 1..0],
      scanoutb[WIDTH_B - 1..0]); 

COMPONENT altmult_accum 
   GENERIC 
      (WIDTH_A                        : INTEGER  := 3;
      WIDTH_B                         : INTEGER  := 3;
      WIDTH_RESULT                    : INTEGER  := 10;
      INPUT_REG_A                     : STRING   := "CLOCK0";
      INPUT_ACLR_A                    : STRING   := "ACLR3";
      INPUT_REG_B                     : STRING   := "CLOCK0";
      INPUT_ACLR_B                    : STRING   := "ACLR3";
      ADDNSUB_REG                     : STRING   := "CLOCK0";
      ADDNSUB_ACLR                    : STRING   := "ACLR3";
      ADDNSUB_PIPELINE_REG            : STRING   := "CLOCK0";
      ADDNSUB_PIPELINE_ACLR           : STRING   := "ACLR3";
      ACCUM_DIRECTION                 : STRING   := "ADD";
      ACCUM_SLOAD_REG                 : STRING   := "CLOCK0";
      ACCUM_SLOAD_ACLR                : STRING   := "ACLR3";
      ACCUM_SLOAD_PIPELINE_REG        : STRING   := "CLOCK0";
      ACCUM_SLOAD_PIPELINE_ACLR       : STRING   := "ACLR3";
      REPRESENTATION_A                : STRING   := "UNSIGNED";
      SIGN_REG_A                      : STRING   := "CLOCK0";
      SIGN_ACLR_A                     : STRING   := "ACLR3";
      SIGN_PIPELINE_REG_A             : STRING   := "CLOCK0";
      SIGN_PIPELINE_ACLR_A            : STRING   := "ACLR3";
      REPRESENTATION_B                : STRING   := "UNSIGNED";
      SIGN_REG_B                      : STRING   := "CLOCK0";
      SIGN_ACLR_B                     : STRING   := "ACLR3";
      SIGN_PIPELINE_REG_B             : STRING   := "CLOCK0";
      SIGN_PIPELINE_ACLR_B            : STRING   := "ACLR3";
      MULTIPLIER_REG                  : STRING   := "CLOCK0";
      MULTIPLIER_ACLR                 : STRING   := "ACLR3";
      OUTPUT_REG                      : STRING   := "CLOCK0";
      OUTPUT_ACLR                     : STRING   := "ACLR0";
      EXTRA_MULTIPLIER_LATENCY        :INTEGER   := 0;
      EXTRA_ACCUMULATOR_LATENCY       :INTEGER   := 0;
      DEDICATED_MULTIPLIER_CIRCUITRY  :STRING    := "AUTO");
 
   PORT (dataa                             : IN STD_LOGIC_VECTOR(NUMBER_OF_MULTIPLIERS * WIDTH_A -1 DOWNTO 0);
         datab                             : IN STD_LOGIC_VECTOR(NUMBER_OF_MULTIPLIERS * WIDTH_B -1 DOWNTO 0);
         addnsub, clock0, clock1, clock2,  
            clock3, ena0, ena1, ena2, ena3 : IN STD_LOGIC := '1';
         accum_sload, signa, signb, aclr0, 
            aclr1, aclr2, aclr3            : IN STD_LOGIC := '0';
         result                            : OUT STD_LOGIC_VECTOR(WIDTH_RESULT -1 DOWNTO 0);
         overflow                          : OUT STD_LOGIC;
         scanouta                          : OUT STD_LOGIC_VECTOR (WIDTH_A -1 DOWNTO 0);
         scanoutb                          : OUT STD_LOGIC_VECTOR (WIDTH_B -1 DOWNTO 0));

END COMPONENT;

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

INPUT PORTS

OUTPUT PORTS

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