See Also

Parameterized multiply-add megafunction. The altmult_add megafunction consists of one or more multipliers feeding a parallel adder.

This topic contains the following information:

• AHDL Function Prototype (also applies to Verilog HDL)
• VHDL Component Declaration
• VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
• Port Descriptions
• Parameter Descriptions

FUNCTION altmult_add (dataa[NUMBER_OF_MULTIPLIERS * WIDTH_A - 1..0], datab[NUMBER_OF_MULTIPLIERS * WIDTH_B - 1..0],
      clock3, clock2, clock1, clock0, aclr3, aclr2, aclr1, aclr0, ena3, ena2, ena1, ena0, signa, signb, addnsub1,
      addnsub3)
   WITH (NUMBER_OF_MULTIPLIERS, WIDTH_A, WIDTH_B, WIDTH_RESULT, INPUT_REGISTER_A0, INPUT_ACLR_A0, INPUT_SOURCE_A0,
      INPUT_REGISTER_A1, INPUT_ACLR_A1, INPUT_SOURCE_A1, INPUT_REGISTER_A2, INPUT_ACLR_A2, INPUT_SOURCE_A2,
      INPUT_REGISTER_A3, INPUT_ACLR_A3, INPUT_SOURCE_A3, REPRESENTATION_A, SIGNED_REGISTER_A, SIGNED_ACLR_A,
      SIGNED_PIPELINE_REGISTER_A, SIGNED_PIPELINE_ACLR_A, INPUT_REGISTER_B0, INPUT_ACLR_B0, INPUT_SOURCE_B0,
      INPUT_REGISTER_B1, INPUT_ACLR_B1, INPUT_SOURCE_B1, INPUT_REGISTER_B2, INPUT_ACLR_B2, INPUT_SOURCE_B2,
      INPUT_REGISTER_B3, INPUT_ACLR_B3, INPUT_SOURCE_B3, REPRESENTATION_B, SIGNED_REGISTER_B, SIGNED_ACLR_B,
      SIGNED_PIPELINE_REGISTER_B, SIGNED_PIPELINE_ACLR_B, MULTIPLIER_REGISTER0, MULTIPLIER_ACLR0,
      MULTIPLIER_REGISTER1, MULTIPLIER_ACLR1, MULTIPLIER_REGISTER2, MULTIPLIER_ACLR2, MULTIPLIER_REGISTER3,
      MULTIPLIER_ACLR3, MULTIPLIER1_DIRECTION, ADDNSUB_MULTIPLIER_REGISTER1, ADDNSUB_MULTIPLIER_ACLR1,
      ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1, ADDNSUB_MULTIPLIER_PIPELINE_ACLR1, MULTIPLIER3_DIRECTION,
      ADDNSUB_MULTIPLIER_REGISTER3, ADDNSUB_MULTIPLIER_ACLR3, ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3,
      ADDNSUB_MULTIPLIER_PIPELINE_ACLR3, OUTPUT_REGISTER, OUTPUT_ACLR, DEDICATED_MULTIPLIER_CIRCUITRY)
   RETURNS (result[WIDTH_RESULT - 1..0], scanouta[WIDTH_A - 1..0], scanoutb[WIDTH_B - 1..0]);

COMPONENT altmult_add 
   GENERIC
      (WIDTH_A                    : INTEGER := 3;
      WIDTH_B                     : INTEGER := 3;
      WIDTH_RESULT                : INTEGER := 16;
      NUMBER_OF_MULTIPLIERS       : INTEGER := 4;
      INPUT_REGISTER_A0           : STRING  := "CLOCK0";
      INPUT_ACLR_A0               : STRING  := "ACLR3";
      INPUT_SOURCE_A0             : STRING  := "DATAA";
      INPUT_REGISTER_A1           : STRING  := "CLOCK0";
      INPUT_ACLR_A1               : STRING  := "ACLR3";
      INPUT_SOURCE_A1             : STRING  := "DATAA";
      INPUT_REGISTER_A2           : STRING  := "CLOCK0";
      INPUT_ACLR_A2               : STRING  := "ACLR3";
      INPUT_SOURCE_A2             : STRING  := "DATAA";
      INPUT_REGISTER_A3           : STRING  := "CLOCK0";
      INPUT_ACLR_A3               : STRING  := "ACLR3";
      INPUT_SOURCE_A3             : STRING  := "DATAA";
      REPRESENTATION_A            : STRING  := "UNSIGNED";
      SIGNED_REGISTER_A           : STRING  := "CLOCK0";
      SIGNED_ACLR_A               : STRING  := "ACLR3";
      SIGNED_PIPELINE_REGISTER_A  : STRING 	:= "CLOCK0";
      SIGNED_PIPELINE_ACLR_A      : STRING  := "ACLR3";
      INPUT_REGISTER_B0           : STRING  := "CLOCK0";
      INPUT_ACLR_B0               : STRING  := "ACLR3";
      INPUT_SOURCE_B0             : STRING  := "DATAB";
      INPUT_REGISTER_B1           : STRING  := "CLOCK0";
      INPUT_ACLR_B1               : STRING  := "ACLR3";
      INPUT_SOURCE_B1             : STRING  := "DATAB";
      INPUT_REGISTER_B2           : STRING  := "CLOCK0";
      INPUT_ACLR_B2               : STRING  := "ACLR3";
      INPUT_SOURCE_B2             : STRING  := "DATAB";
      INPUT_REGISTER_B3           : STRING  := "CLOCK0";
      INPUT_ACLR_B3               : STRING  := "ACLR3";
      INPUT_SOURCE_B3             : STRING  := "DATAB";
      REPRESENTATION_B            : STRING  := "UNSIGNED";
      SIGNED_REGISTER_B           : STRING  := "CLOCK0";
      SIGNED_ACLR_B               : STRING  := "ACLR3";
      SIGNED_PIPELINE_REGISTER_B  : STRING  := "CLOCK0";
      SIGNED_PIPELINE_ACLR_B      : STRING  := "ACLR3";
      MULTIPLIER_REGISTER0        : STRING  := "CLOCK0";
      MULTIPLIER_ACLR0            : STRING  := "ACLR3";
      MULTIPLIER_REGISTER1        : STRING  := "CLOCK0";
      MULTIPLIER_ACLR1            : STRING  := "ACLR3";
      MULTIPLIER_REGISTER2        : STRING  := "CLOCK0";
      MULTIPLIER_ACLR2            : STRING  := "ACLR3";
      MULTIPLIER_REGISTER3        : STRING  := "CLOCK0";
      MULTIPLIER_ACLR3            : STRING  := "ACLR3";
      ADDNSUB_MULTIPLIER_REGISTER1             : STRING := "CLOCK0";
      ADDNSUB_MULTIPLIER_ACLR1                 : STRING := "ACLR3";
      ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1    : STRING := "CLOCK0";
      ADDNSUB_MULTIPLIER_PIPELINE_ACLR1        : STRING := "ACLR3";
      ADDNSUB_MULTIPLIER_REGISTER3             : STRING := "CLOCK0";
      ADDNSUB_MULTIPLIER_ACLR3                 : STRING := "ACLR3";
      ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3    : STRING := "CLOCK0";
      ADDNSUB_MULTIPLIER_PIPELINE_ACLR3        : STRING := "ACLR3";
      MULTIPLIER1_DIRECTION                    : STRING := "ADD";
      MULTIPLIER3_DIRECTION                    : STRING := "ADD";
      OUTPUT_REGISTER                          : STRING := "CLOCK0";
      OUTPUT_ACLR                              : STRING := "ACLR0"; 
      DEDICATED_MULTIPLIER_CIRCUITRY           :STRING  := "AUTO");

   PORT (dataa                           : IN STD_LOGIC_VECTOR(NUMBER_OF_MULTIPLIERS * NUMBER_OF_MULTIPLIERS * WIDTH_A -1 DOWNTO 0);
        datab                            : IN STD_LOGIC_VECTOR(NUMBER_OF_MULTIPLIERS * WIDTH_B -1 DOWNTO 0);
        clock3, clock2, clock1, clock0   : IN STD_LOGIC := '1';
        aclr3, aclr2, aclr1, aclr0       : IN STD_LOGIC := '0';
        ena3, ena2, ena1, ena0           : IN STD_LOGIC := '1';
        signa, signb                     : IN STD_LOGIC := '0';
        addnsub1, addnsub3               : IN STD_LOGIC := 'Z';
        result                           : OUT STD_LOGIC_VECTOR(WIDTH_RESULT -1 DOWNTO 0);
        scanouta                         : OUT STD_LOGIC_VECTOR (WIDTH_A -1 DOWNTO 0);
        scanoutb                         : OUT STD_LOGIC_VECTOR (WIDTH_B -1 DOWNTO 0));

END COMPONENT;

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

INPUT PORTS

OUTPUT PORTS

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