Megafunctions

altddio_bidir (DDIO Bidirectional) Megafunction

Double Data Rate (DDR) bidirectional megafunction. The altddio_bidir megafunction transmits and receives data on both edges of the reference clock. The altddio_bidir megafunction is available for APEX™ II, Cyclone™, Mercury™, Stratix™, and Stratix™ GX devices only.

This topic contains the following information:


AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION altddio_bidir (datain_h[(WIDTH) - (1)..0], datain_l[(WIDTH) - (1)..0], 
      inclock, inclocken, outclock, outclocken, oe, aclr, aset)
   WITH (WIDTH, POWER_UP_HIGH, OE_REG, EXTEND_OE_DISABLE, IMPLEMENT_INPUT_IN_LCELL, INTENDED_DEVICE_FAMILY)
   RETURNS (dataout_h[(WIDTH) - (1)..0], dataout_l[(WIDTH) - (1)..0], 
      combout[(WIDTH) - (1)..0], padio[(WIDTH) - (1)..0]);


VHDL Component Declaration:

 
COMPONENT altddio_bidir
    GENERIC 
       (WIDTH                       : POSITIVE	:= 1;
        POWER_UP_HIGH	            : STRING  	:= "OFF"
        OE_REG                      : STRING  	:= "UNUSED"
        IMPLEMENT_INPUT_IN_LCELL    : STRING   := "UNUSED"		
        EXTEND_OE_DISABLE           : STRING  	:= "UNUSED");
		
    PORT (data_in_h, data_in_l 	        : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
          inclock, outclock, oe         : IN STD_LOGIC;
          inclocken, outclocken         : IN STD_LOGIC := 1; 
          aclr, aset, oe                : IN STD_LOGIC := 0;
          dataout_h, dataout_l, combout : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
          padout                        : INOUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
END COMPONENT;


Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
datain_h[] Yes Input data to be output to the padio port at the rising edge of the outclock port. Input port WIDTH wide.
datain_l[] Yes Input data to be output to the padio port at the falling edge of the outclock port. Input port WIDTH wide.
inclock Yes Clock signal to sample the DDR input. The padio port is sampled on each clock edge of the inclock signal.
inclocken No Clock enable for the DDR clock.  
outclock Yes Clock signal to register the data output. The padio port outputs the DDR data on each edge of the outclock clock signal.
outclocken No Clock enable for the outclock port.  
aclr No Asynchronous clear input. The aclr port and the aset port cannot be connected at the same time.
aset No Asynchronous set input. The aclr port and the aset port cannot be connected at the same time.
oe No Output enable for the bidirectional padio port. If the oe port is not connected, then the padio port is an output port.

OUTPUT PORTS

Port Name Required Description Comments
dataout_h[] Yes Data sampled from the padio port at the rising edge of the inclock signal.  
dataout_l[] Yes Data sampled from the padio port at the falling edge of the inclock signal.  
combout[] No Combinatorial output directly fed by the padio port. The combout[] port is available for APEX II, Cyclone, Stratix, and Stratix GX devices only.

BIDIRECTIONAL PORTS

Port Name Required Description Comments
padio Yes Bidirectional DDR port that should directly feed a bidirectional pin in the top-level design. The DDR data is transmitted and received on this bidirectional port.


Parameter Descriptions:
Parameter Type Required Comments
WIDTH Integer Yes Width of the datain_h, datain_l, and dataout ports.
POWER_UP_HIGH String No When both the aset and aclr ports are unused, the POWER_UP_HIGH parameter is available to specify the power-up state of the output ports. Values are "ON", and "OFF". If omitted, the default is "OFF".
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. Create the altddio_bidir megafunction with the MegaWizard® Plug-in Manager (Tools menu) to calculate the value for this parameter.
OE_REG String No Specifies whether the oe port is registered. Values are "REGISTERED", "UNREGISTERED", and "UNUSED". If omitted, the default is "UNUSED". This parameter is available for APEX II devices only.
IMPLEMENT_INPUT_IN_LCELL String No Specifies whether the input channels should be implemented using logic cells. Values are "ON", "OFF", and "UNUSED". If omitted, the default is "UNUSED". This parameter is available for APEX II devices only.
EXTEND_OE_DISABLE String No Specifies whether the second oe register should be used. When the second oe register is used, the output pin is held at high impedance for an extra half clock cycle after the oe port goes high. Values are "ON", "OFF", and "UNUSED". If omitted, the default is "UNUSED". This parameter is available for APEX II devices only.


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