Megafunctions

altcdr_tx (CDR) Megafunction
NOTE CDR functionality is disabled in this release. Designing with CDR can be support intensive and requires close engagement with Altera® early in the design cycle. Please contact your Altera representative to discuss support requirements.

Clock Data Recovery (CDR) transmitter megafunction. The altcdr_tx megafunction implements a CDR transmitter. The altcdr_tx megafunction uses CDR transmitter circuitry for serialization, as well as a FIFO to match clock domains. The altcdr_tx megafunction is available for Mercury™ devices only.

This topic contains the following information:


AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION altcdr_tx (tx_in[((DESERIALIZATION_FACTOR) * (NUMBER_OF_CHANNELS)) - (1)..0], 
      tx_inclock, tx_coreclock, tx_aclr, tx_pll_aclr, 
      tx_fifo_wren[(NUMBER_OF_CHANNELS) - (1)..0])
   WITH (NUMBER_OF_CHANNELS, DESERIALIZATION_FACTOR, INCLOCK_PERIOD, INCLOCK_BOOST, BYPASS_FIFO,
      INTENDED_DEVICE_FAMILY)
   RETURNS (tx_out[(NUMBER_OF_CHANNELS) - (1)..0], tx_outclock, tx_pll_locked, 
      tx_full[(NUMBER_OF_CHANNELS) - (1)..0], tx_empty[(NUMBER_OF_CHANNELS) - (1)..0]);


VHDL Component Declaration:

 
COMPONENT altcdr_tx
    GENERIC 
       (NUMBER_OF_CHANNELS	: POSITIVE := 1;
        DESERIALIZATION_FACTOR 	: POSITIVE := 1;
        INCLOCK_PERIOD		: POSITIVE;
        INCLOCK_BOOST		: POSITIVE := 1
        BYPASS_FIFO	        : STRING   := "OFF");
		
    PORT (tx_in : IN STD_LOGIC_VECTOR(DESERIALIZATION_FACTOR*NUMBER_OF_CHANNELS-1 DOWNTO 0);
          tx_inclock, tx_coreclock, tx_aclr, tx_pll_aclr  : IN STD_LOGIC;
          tx_fifo_wren : IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS DOWNTO 0);
          tx_out, tx_empty, tx_full : OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
          tx_outclock, tx_pll_locked : OUT STD_LOGIC;
END COMPONENT;


Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
tx_in[] Yes Input data. Input port [DESERIALIZATION_FACTOR * NUMBER_OF_CHANNELS-1..0] wide.
tx_inclock Yes CDR reference input clock.  
tx_coreclock Yes Clock used to write data to the transmitter channel from non-peripheral logic.  
tx_fifo_wren[] No Write enable control for writing to the transmitter channel synchronizing FIFO. Input port [NUMBER_OF_CHANNELS-1..0] wide.
tx_aclr No Asynchronous clear for the transmitter channel and its associated synchronizing FIFO.  
tx_pll_aclr No Asynchronous clear for the transmitter channel PLL.  

OUTPUT PORTS

Port Name Required Description Comments
tx_out[] Yes Serialized CDR data signal. Output port [NUMBER_OF_CHANNELS-1..0] wide. After deserialization, tx_out[n-1] is the first bit transmitted and tx_out[0] is the last bit transmitted for channel one; for channel two, tx_out[2n-1] is the first bit transmitted and tx_out[n] is the last bit transmitted. For more information on bit order, see Application Note 120 (Using LVDS in APEX™ 20KE Devices).
tx_outclock No External reference clock. This port can only be used to feed internal logic and cannot be connected to an output pin. Period equals [INCLOCK_PERIOD / INCLOCK_BOOST] * DESERIALIZATION_FACTOR.
tx_pll_locked No Specifies whether the transmitter channel PLL is locked on the tx_inclock clock.  
tx_empty[] No If asserted, indicates that the transmitter channel synchronizing fifo is empty. Output port [NUMBER_OF_CHANNELS-1..0] wide. The non-peripheral logic should check this signal to avoid a transmission under run.
tx_full[] No If asserted, indicates that the transmitter channel synchronizing FIFO is full. Output port [NUMBER_OF_CHANNELS-1..0] wide. The non-peripheral logic should check this signal to avoid a transmission over run and stop sending data.


Parameter Descriptions:
Parameter Type Required Comments
NUMBER_OF_CHANNELS Integer Yes Specifies the number of CDR channels.
DESERIALIZATION_FACTOR Integer Yes Specifies the number of bits per channel. Values are 3-12, 14, or 16, 18, and 20. The value of the INCLOCK_PERIOD parameter is between [125 MHz / DESERIALIZATION_FACTOR] and [1250 MHz / DESERIALIZATION_FACTOR].
INCLOCK_PERIOD Integer Yes Specifies the period or frequency of the input clock. The default time unit is picoseconds (ps). In AHDL designs only, strings, such as 50.5 MHz, are acceptable.
INCLOCK_BOOST Integer No The effective clock period used to sample output data is INCLOCK_PERIOD / INCLOCK_BOOST].
BYPASS_FIFO String No Specifies whether the transmitter channel sychronizing FIFO should be instantiated, and whether the serialization channel outputs are directly connected to output ports.
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. Create the PLL with the MegaWizard® Plug-in Manager to calculate the value for this parameter.


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