altcdr_rx Megafunction

altcdr_rx (CDR) Megafunction

CDR functionality is disabled in this release. Designing with CDR can be support intensive and requires close engagement with Altera^® early in the design cycle. Please contact your Altera representative to discuss support requirements.

Clock Data Recovery (CDR) receiver megafunction. The altcdr_rx megafunction implements a CDR receiver. The altcdr_rx megafunction uses CDR receiver circuitry for deserialization, and contains a digital phase-locked loop (PLL) to compensate for channel-to-clock and channel-to-channel skew, as well as a FIFO to match clock domains. The altcdr_rx megafunction is available for Mercury^™ devices only.

This topic contains the following information:

AHDL Function Prototype (also applies to Verilog HDL)
VHDL Component Declaration
Port Descriptions
Parameter Descriptions

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION altcdr_rx (rx_in[(NUMBER_OF_CHANNELS) - (1)..0], rx_inclock, rx_coreclock, 
      rx_aclr, rx_pll_aclr, rx_fifo_rden[(NUMBER_OF_CHANNELS) - (1)..0])
   WITH (NUMBER_OF_CHANNELS, DESERIALIZATION_FACTOR, INCLOCK_PERIOD, INCLOCK_BOOST, 
      RUN_LENGTH, BYPASS_FIFO, INTENDED_DEVICE_FAMILY)
   RETURNS (rx_out[((DESERIALIZATION_FACTOR) * (NUMBER_OF_CHANNELS)) - (1)..0], rx_outclock,
      rx_locklost[(NUMBER_OF_CHANNELS) - (1)..0], rx_pll_locked, rx_rlv[(NUMBER_OF_CHANNELS) - (1)..0], rx_rec_clk[(NUMBER_OF_CHANNELS) - (1)..0],
      rx_full[(NUMBER_OF_CHANNELS) - (1)..0], rx_empty[(NUMBER_OF_CHANNELS) - (1)..0]);

VHDL Component Declaration:

COMPONENT altcdr_rx
    GENERIC 
       (NUMBER_OF_CHANNELS	: POSITIVE := 1;
        DESERIALIZATION_FACTOR 	: POSITIVE := 1;
        INCLOCK_PERIOD		: POSITIVE;
        RUN_LENGTH		: INTEGER  := 1;
        INCLOCK_BOOST		: POSITIVE := 1
        BYPASS_FIFO	        : STRING   := "OFF");
		
    PORT (rx_in : IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
          rx_inclock, rx_coreclock, rx_aclr, rx_pll_aclr  : IN STD_LOGIC;
          rx_fifo_rden : IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS DOWNTO 0);
          rx_out : OUT STD_LOGIC_VECTOR(DESERIALIZATION_FACTOR*NUMBER_OF_CHANNELS-1 DOWNTO 0);
          rx_outclock, rx_pll_locked : OUT STD_LOGIC;
          rx_locklost, rx_rec_clk, rx_empty, rx_full, rx_rlv  : OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
END COMPONENT;

Port Descriptions:

INPUT PORTS

Port Name	Required	Description	Comments
`rx_in[]`	Yes	CDR serial input data port.	Input port `[NUMBER_OF_CHANNELS-1..0]` wide. After deserialization, `rx_in[n-1]` is the first bit received and `rx_in[0]` is the last bit received for channel one; for channel two, `rx_in[2n-1]` is the first bit received and `rx_in[n]` is the last bit received. For more information on bit order, see Application Note 120 (Using LVDS in APEX^™ 20KE Devices).
`rx_inclock`	Yes	CDR reference input clock.
`rx_coreclock`	Yes	Clock used to read data from the receiver channel FIFO(s) into the non-peripheral logic.
`rx_fifo_rden[]`	No	Read enable control for reading from the receiver channel synchronizing FIFO(s).	Input port `[NUMBER_OF_CHANNELS-1..0]` wide. If asserted, enables reading from the corresponding receiver channel FIFO.
`rx_aclr`	No	Asynchronous clear for the receiver channel and its associated synchronizing FIFO.
`rx_pll_aclr`	No	Asynchronous clear for the receiver channel PLL.

OUTPUT PORTS

Port Name	Required	Description	Comments
`rx_out[]`	Yes	Deserialized data signal.	Output port `[DESERIALIZATION_FACTOR * NUMBER_OF_CHANNELS-1..0]` wide.
`rx_rec_clk[]`	No	Recovered data clock from all receiver channels which drive priority column routing resources.	Output port `[NUMBER_OF_CHANNELS-1..0]` wide. The `rx_rec_clk` period varies based on the data rate, but is approximately `[INCLOCK_PERIOD / INCLOCK_BOOST] * DESERIALIZATION_FACTOR`.
`rx_outclock`	No	Recovered data clock from receiver channel `0` that drives to a global clock.	The `rx_outclock` period varies based on the data rate, but is approximately `[INCLOCK_PERIOD / INCLOCK_BOOST] * DESERIALIZATION_FACTOR`.
`rx_locklost[]`	No	Specifies whether a receiver channel has lost the lock with the incoming input data signal.	Output port `[NUMBER_OF_CHANNELS-1..0]` wide. When asserted, indicates the receiver channel was not successful in synchronizing itself with the incoming input signal and is not able to sample the data accurately.
`rx_pll_locked`	No	Specifies whether the receiver channel PLL is locked on the `rx_inclock` input.
`rx_empty[]`	No	If asserted, indicates that the receiver channel synchronizing FIFO is empty.	Input port `[NUMBER_OF_CHANNELS-1..0]` wide. Non-peripheral logic should check this signal to make sure the receiver channel has valid data to read.
`rx_full[]`	No	If asserted, indicates that the receiver channel synchronizing FIFO is full.	Input port `[NUMBER_OF_CHANNELS-1..0]` wide. The non-peripheral logic should check this signal to detect an overflow condition in the synchronizing FIFO and request a retransmission of data if needed.
`rx_rlv`	No	Specifies a run-length requirement violation of the input data signal.	The non-peripheral logic should check this signal to detect a run length violation by the input data signal. This signal will be asserted if the input data does not transition frequently enough for the receiver channel to maintain synchronization.

Parameter Descriptions:

Parameter	Type	Required	Comments
`NUMBER_OF_CHANNELS`	Integer	Yes	Specifies the number of CDR channels
`DESERIALIZATION_FACTOR`	Integer	Yes	Specifies the number of bits per channel. Values are `3-12`, `14`, or `16`, `18`, and `20`. The value of the `INCLOCK_PERIOD` parameter is between `[125 MHz / DESERIALIZATION_FACTOR] and [1250 MHz / DESERIALIZATION_FACTOR]`.
`INCLOCK_PERIOD`	Integer	Yes	Specifies the period or frequency of the input clock. The default time unit is picoseconds (ps). In AHDL designs only, strings, such as 50.5 MHz, are acceptable.
`RUN_LENGTH`	Integer	No	Specifies the maximum run length allowed for the incoming data signal.
`INCLOCK_BOOST`	Integer	No	The effective clock period used to sample output data is `INCLOCK_PERIOD / INCLOCK_BOOST]`.
`BYPASS_FIFO`	String	No	Specifies whether the receiver channel sychronizing FIFO should be instantiated, and whether the deserialization channel outputs are directly connected to output ports. Values are `"ON"` and `"OFF"`. If omitted, the default is `"OFF"`. When this parameter is set to `"ON"` the `rx_coreclock` port must be used. When this parameter is set to `"OFF"` the `rx_coreclock` port must be used if the `rx_rlv` or `rx_locklost[]` ports are used.
`INTENDED_DEVICE_FAMILY`	String	No	This parameter is used for modeling and behavioral simulation purposes. Create the PLL with the MegaWizard^® Plug-in Manager to calculate the value for this parameter.

This topic prints best in Landscape orientation.

- PLDWorld -

Created by chm2web html help conversion utility.