You can perform a functional simulation of an Excalibur design before compilation and synthesis in the Quartus II software. To do this, you must first generate an uPCore Transaction Model Input File (.mbus_in) that describes the embedded processor bus transactions over the Stripe-To-PLD Bridge via the Stripe Master Port. You can then use the Quartus II Simulator, in addition to the bus functional model, to perform a functional simulation of the design and generate an uPCore Transaction Model Output File (.mbus_out) that lists the bus transactions between the PLD and the stripe.
|