Primitive

TRI Primitive



AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION TRI (in, oe)
   RETURNS (out);


VHDL Component Declaration:

COMPONENT TRI
   PORT (a_in : IN STD_LOGIC;
      oe: IN STD_LOGIC;
      a_out: OUT STD_LOGIC);
END COMPONENT;

The TRI primitive is a tri-state buffer with an input, output, and output enable signal. If the output enable input to the TRI buffer is high, the output will be driven by the Input.

The output enable defaults to VCC.

If the output enable of a TRI buffer is connected to VCC or a logic function that will minimize to true, a TRI buffer may be converted into a SOFT buffer during logic synthesis. In ACEX® 1K, APEX 20KC, APEX 20KC, APEX II, ARM®-based Excalibur, Cyclone, FLEX 10KE, Mercury, Stratix, and Stratix GX projects, some configurations of TRI primitives and other logic are automatically converted into OPNDRN buffers.

When you use a TRI buffer, you must observe the following rules in addition to the rules listed in Primitive/Port Interconnections:


Inputs
IN OE
Output
OUT
X 0 Z
1 1 1
0 1 0


Back to Top

- PLDWorld -

 

Created by chm2web html help conversion utility.