Megafunction

lpm_compare (Comparator) Megafunction

Parameterized comparator megafunction. Altera® recommends that you use the lpm_compare function instead of any other type of comparator.

Altera also recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

NOTE The lpm_compare megafunction normally limits cascade chain lengths to the value specified by the Cascade Chain Length option, which has a default value of two. Increasing this value may increase circuit performance, but may make it more difficult for the Fitter to fit the circuit into the specified device.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_compare (dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0], clock, aclr, clken)
   WITH (LPM_WIDTH, LPM_REPRESENTATION, LPM_PIPELINE, CHAIN_SIZE, ONE_INPUT_IS_CONSTANT)
   RETURNS (alb, aeb, agb, ageb, aneb, aleb);

 

VHDL Component Declaration:

 
COMPONENT lpm_compare
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_REPRESENTATION: STRING := "UNSIGNED";
      LPM_PIPELINE: INTEGER := 0;
      LPM_TYPE: STRING := "LPM_COMPARE";
      LPM_HINT: STRING := "UNUSED");
   PORT (dataa, datab: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      aclr, clock: IN STD_LOGIC := '0';
	  clken: IN STD_LOGIC := '1';
      agb, ageb, aeb, aneb, alb, aleb: OUT STD_LOGIC);
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
dataa[] Yes Value to be compared to datab[]. Input port LPM_WIDTH wide.
datab[] Yes Value to be compared to dataa[]. Input port LPM_WIDTH wide.
clock No Clock for pipelined usage. The clock port provides pipelined operation for the lpm_compare function. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected.
clken No Clock enable for pipelined usage. If omitted, the default is 1.
aclr No Asynchronous clear for pipelined usage. The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to the clock signal.

OUTPUT PORTS

Port Name Required Description Comments
alb No High (1) if dataa[] < datab[]. One of alb, aeb, agb, ageb, aleb, or aneb must be present.
aeb No High (1) if dataa[] == datab[]. One of alb, aeb, agb, ageb, aleb, or aneb must be present.
agb No High (1) if dataa[] > datab[]. One of alb, aeb, agb, ageb, aleb, or aneb must be present.
ageb No High (1) if dataa[] >= datab[]. One of alb, aeb, agb, ageb, aleb, or aneb must be present.
aneb No High (1) if dataa[] != datab[]. One of alb, aeb, agb, ageb, aleb, or aneb must be present.
aleb No High (1) if dataa[] <= datab[]. One of alb, aeb, agb, ageb, aleb, or aneb must be present.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the dataa[] and datab[] ports.
LPM_REPRESENTATION String No Type of comparison performed: "SIGNED", "UNSIGNED", or "UNUSED". If omitted, the default is "UNSIGNED". The signed representation for all library of parameterized modules (LPM) megafunctions is two's complement.
LPM_PIPELINE Integer No Specifies the number of Clock cycles of latency associated with the alb, aeb, agb, ageb, aleb, or aneb output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default value is 0 (non-pipelined).
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.
CHAIN_SIZE Integer No Altera-specific parameter. Maximum allowable length of carry chains or cascade chains in ACEX® 1K, APEX™ 20K, APEX™ II, ARM®-based Excalibur™, FLEX® 6000, FLEX 10KE, and Mercury™ devices. If omitted, the default is 8. This value overrides the value of the Carry Chain Length and Cascade Chain Length logic options specified with the Assignment Organizer dialog box (Assignment menu). For all other device families, varying this parameter provides different size/speed combinations; smaller values of CHAIN_SIZE generally result in faster and larger comparators, and vice versa. For more information, contact Altera Applications.
ONE_INPUT_IS_CONSTANT String No Altera-specific parameter. Values are "YES", "NO", or "UNUSED". Provides greater optimization if an input is constant. If omitted, the default is "NO".

 

Truth Table/Functionality:
Inputs Outputs
dataa[LPM_WIDTH-1..0] datab[LPM_WIDTH-1..0] alb aeb agb ageb aleb aneb
a b a < b a == b a > b a >= b a <= b a != b

 

Resource Usage:

The following table summarizes the resource usage for an lpm_compare function used to implement a 16-bit unsigned comparator. Logic cell usage scales linearly in proportion to shifter width.

Design Goals Design Results
Device Family Optimization
APEX 20K Routability
  Speed
Width Logic Cells
16 25
16 17

Numbers of shared expanders used are shown in parentheses ( ).

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