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To compile a design:

1. If you have not already done so, create a new project or open an existing project.

2. Specify Compiler settings.

3. If you are using the Timing Analyzer, specify the timing analysis settings using the steps in the following procedures:

• Creating Clock Settings
• Assigning Clock Settings to a Clock Signal
• Specifying Project-Wide Timing Requirements

• Making Individual Timing Assignments

4. If necessary, specify the user libraries for the project and the order in which the Compiler searches the libraries.

5. If the project contains one or more VHDL Design Files (.vhd), specify the VHDL Version and Library Mapping File (.lmf) for compiling VHDL Design Files.

6. If the project contains one or more Verilog Design Files (.v), specify options for compiling Verilog Design Files.

7. If the project contains one or more EDIF Input Files (.edf) or Verilog Quartus^® Mapping Files (.vqm), specify the EDA input settings for the project.

8. If you want to generate Verilog Output Files (.vo) and corresponding Standard Delay Format Output Files (.sdo), or VHDL Output Files (.vho) and corresponding SDF Output Files, specify a simulation or timing analysis tool that supports Verilog HDL or VHDL and specify Verilog HDL output settings or VHDL output settings. More Details

9. If you want to generate IBIS Output Files (.ibs) or PartMiner XML-Format Files (.xml), specify a board-level verification tool. If necessary, specify IBIS output settings. More Details

10. If necessary, specify that the Quartus^® II software automatically save changes to all open files or ask you whether you want to save changes to each open file before starting a compilation.

11. Start the compilation.  More Details

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