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When simulating a vector file that contains bidirectional nodes, use the following guidelines:
A bidirectional node is represented in a Vector Waveform File (.vwf) by two channels: one channel represents the input to the bidirectional node, the other channel represents the output from the bidirectional node. You can enter the input channel into the VWF by adding the bidirectional node to the VWF using the Node Finder dialog box, or you can insert the bidirectional node into the VWF using the Insert Node or Bus command (Edit menu).
If the Automatically add pins to simulation output waveforms option is turned on, the Simulator automatically creates the corresponding output channel for the bidirectional node, named <bidir node name>~result, after simulation is complete. This channel contains the logic levels of the output channel during simulation. Alternatively, you can manually create the output channel and specify the expected logic levels for the output channel. If you manually create the channel, you must name the channel <bidir node name>~result, and follow the additional guidelines below about specifying the logic levels of bidirectional nodes.
You should specify a logic level for the bidirectional node even if the tri-state that feeds the bidirectional node is always enabled. You can specify a constant logic level of high impedance (Z), weak low (L), or weak high (H) for the channel. However, if you don't specify a logic level, the Simulator will assume the logic level is forcing unknown (X), which typically produces unexpected results.
If a tri-state buffer that feeds a bidirectional node is enabled, the logic level of the bidirectional node must be high impedance (Z) or a weak signal—for example, weak low (L), weak high (H), or weak unknown (W). If the bidirectional node does not have the correct logic level, the Simulator could produce an error if there is logic contention. For example, if the logic level at the output of the tri-state buffer is different— strong high (1)—from the logic level that the bidirectional channel drives in—strong low (0), the Simulator produces an error.
If the tri-state buffer that feeds a bidirectional node is disabled, the logic level of the bidirectional node must not be high impedance (Z), because the Simulator propagates a forced unknown (X) logic level. If the logic level of the bidirectional node is any of the weak signals, for example, weak low (L), weak high (H), or weak unknown (W), the Simulator uses them as strong signals once the signals propagate through the device.
The input channel cannot be written to by the simulator. Thus, if an output node named "a" and an input channel named "a" exist in the waveform, simulation will fail.
When reading MAX+PLUS® II Vector Files (.vec), the Quartus® Simulator automatically creates the <bidir node name>~result channel for the corresponding bidirectional input channel. The following table shows how the Quartus® II Simulator interprets MAX+PLUS II–style bidirectional channels:
| MAX+PLUS II Bidirectional Channel | Quartus II Bidirectional Channel | ||
|---|---|---|---|
| Node Name | Node Type | Node Name | Node Type |
a |
input | a |
bidir |
a |
output | a~result |
output |
In the previous example, the Simulator reads "a" as an input node if it is not a bidirectional node in the VEC File.
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