See Also

Verilog Design Files (.v) can be combined with other Verilog Design Files, VHDL Design Files (.vhd), Text Design Files (.tdf), Block Design Files (.bdf), and EDIF Input Files (.edf) into a hierarchical project at any level of the project hierarchy. Lower-level files in a project hierarchy can be Altera-provided megafunctions, or user-defined megafunctions or macrofunctions.

The Quartus^® II software provides primitives, as well as bus and architecture-optimized megafunctions. You can use Module Instantiations to insert instances of any supported logic function (that is, primitives, megafunctions, and user-defined macrofunctions). If a Verilog Design File contains non-Quartus II function(s) that need to be mapped to Quartus II functions, you must use the Verilog HDL Input page of the Settings dialog box (Assignments menu) to specify a Library Mapping File (.lmf) for the file.

This section includes the following topics:

• Using a Quartus II Logic Function
• Using a Verilog HDL Gate Primitive
• Implementing a User-Defined Megafunction or Macrofunction
• Using Parameterized Functions
• Implementing CAM, RAM & ROM
• Implementing Inferred RAM

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