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Commands

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To modify an existing project:

1. If you have not already done so, open an existing project.

2. Choose Settings (Assignments menu).  Shortcut

3. Add or remove files.

4. Specify user libraries.

5. Specify the toolset directory.

6. Specify the Library Mapping File (.lmf) and VHDL version for compiling or simulating VHDL input files.

7. Specify the Library Mapping File (.lmf) for compiling or simulating Verilog HDL input files.

8. Specify settings for EDA tools.

9. Specify settings for logic synthesis and fitting options.

10. Add or delete global project parameters.

11. Specify project-wide timing requirements.

12. Specify Compiler settings.

13. Specify Simulator settings.

14. Specify software build settings.

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