lpm_constant Megafunction

lpm_constant (Constant Generator) Megafunction

Parameterized constant generator megafunction. Altera^® recommends using the CONSTANT primitive or AHDL Constant Statements rather than lpm_constant for easier implementation and to improve compilation time. However, lpm_constant may be useful if you need to convert a parameter into a constant.

Altera also recommends instantiating this function as described in Using the MegaWizard^® Plug-In Manager.

This topic contains the following information:

AHDL Function Prototype (also applies to Verilog HDL)
VHDL Component Declaration
VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
Port Descriptions
Parameter Descriptions
Resource Usage

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_constant ( )
   WITH (LPM_WIDTH, LPM_CVALUE)
   RETURNS (result[LPM_WIDTH-1..0]);

VHDL Component Declaration:

COMPONENT lpm_constant
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_CVALUE: NATURAL;
      LPM_STRENGTH: STRING := "UNUSED";
      LPM_TYPE: STRING := "LPM_CONSTANT";
      LPM_HINT: STRING := "UNUSED");
   PORT (result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

VHDL LIBRARY-USE Declaration

LIBRARY lpm;
USE lpm.lpm_components.all;

Port Descriptions:

OUTPUT PORTS

Port Name	Required	Description	Comments
`result[]`	Yes	Value specified by the argument to `LPM_CVALUE`.	Output port `LPM_WIDTH` bits wide. `LPM_CVALUE` is truncated or sign-extended to `LPM_WIDTH` bits.

Parameter Descriptions:

Parameter	Type	Required	Description
`LPM_WIDTH`	Integer	Yes	Width of the `result[]` port.
`LPM_CVALUE`	Integer	Yes	Constant value to be driven out on the `result[]` port. If `LPM_CVALUE` cannot be represented in `LPM_WIDTH` bits, the `result[]` port drives the value `LPM_CVALUE` mod 2 ^ `LPM_WIDTH`.
`LPM_HINT`	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is `"UNUSED"`.
`LPM_TYPE`	String	No	Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

Resource Usage:

Uses no resources (that is, 0 logic cells). The constant outputs are absorbed by other logic.

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