Megafunctions

altpll (Phase-Locked Loop) Megafunction

Parameterized phase-locked loop (PLL) megafunction. The altpll megafunction enables PLL circuitry. The phase-locked loop is used to synthesize a clock signal that is based on a reference clock. The altpll megafunction can reduce clock delay and skew, and can be used to generate internal clocks that operate at frequencies that are multiples of the frequency of the system clock. The altpll megafunction can also improve setup and hold times. The Cyclone™ and Stratix™ PLLs have the ability to simultaneously multiply and divide the reference clock, provide an arbitrary phase shift, provide an external clock, and synchronize via an external feedback input.

NOTE The Cyclone PLL uses a subset of the ports and parameters of the altpll megafunction. Altera® recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:


AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION altpll (inclk[1..0], fbin, pllena, clkswitch, areset, pfdena, clkena[5..0],
      extclkena[3..0], scanclk, scanaclr, scandata )
   WITH (OPERATION_MODE, PLL_TYPE, COMPENSATE_CLOCK, SCAN_CHAIN,
      CLK5_MULTIPLY_BY, CLK4_MULTIPLY_BY, CLK3_MULTIPLY_BY, CLK2_MULTIPLY_BY, 
      CLK1_MULTIPLY_BY, CLK0_MULTIPLY_BY, CLK5_DIVIDE_BY, CLK4_DIVIDE_BY, 
      CLK3_DIVIDE_BY, CLK2_DIVIDE_BY, CLK1_DIVIDE_BY, CLK0_DIVIDE_BY, CLK5_PHASE_SHIFT,
      CLK4_PHASE_SHIFT, CLK3_PHASE_SHIFT, CLK2_PHASE_SHIFT, CLK1_PHASE_SHIFT, 
      CLK0_PHASE_SHIFT, CLK5_TIME_DELAY, CLK4_TIME_DELAY, CLK3_TIME_DELAY, CLK2_TIME_DELAY,
      CLK1_TIME_DELAY, CLK0_TIME_DELAY, CLK5_DUTY_CYCLE, CLK4_DUTY_CYCLE, CLK3_DUTY_CYCLE,
      CLK2_DUTY_CYCLE, CLK1_DUTY_CYCLE, CLK0_DUTY_CYCLE, EXTCLK3_MULTIPLY_BY, 
      EXTCLK2_MULTIPLY_BY, EXTCLK1_MULTIPLY_BY, EXTCLK0_MULTIPLY_BY, EXTCLK3_DIVIDE_BY,
      EXTCLK2_DIVIDE_BY, EXTCLK1_DIVIDE_BY, EXTCLK0_DIVIDE_BY, EXTCLK3_PHASE_SHIFT,
      EXTCLK2_PHASE_SHIFT, EXTCLK1_PHASE_SHIFT, EXTCLK0_PHASE_SHIFT, EXTCLK3_TIME_DELAY,
      EXTCLK2_TIME_DELAY, EXTCLK1_TIME_DELAY, EXTCLK0_TIME_DELAY, EXTCLK3_DUTY_CYCLE,
      EXTCLK2_DUTY_CYCLE, EXTCLK1_DUTY_CYCLE, EXTCLK0_DUTY_CYCLE, PRIMARY_CLOCK,
      INCLK0_INPUT_FREQUENCY, INCLK1_INPUT_FREQUENCY, GATE_LOCK_SIGNAL, GATE_LOCK_COUNTER,
      LOCK_HIGH, LOCK_LOW, SWITCH_OVER_ON_LOSSCLK, ENABLE_SWITCH_OVER_COUNTER, 
      SWITCH_OVER_COUNTER, FEEDBACK_SOURCE, BANDWDTH, BANDWIDTH_TYPE, SPREAD_FREQUENCY,
      DOWN_SPREAD, VCO_MIN, VCO_MAX, VCO_CENTER, PFD_MIN, PFD_MAX, M_INITIAL, M, N, M2, 
      N2, SS, L0_HIGH, L1_HIGH, G0_HIGH, G1_HIGH, G2_HIGH, G3_HIGH, E0_HIGH, E1_HIGH, 
      E2_HIGH, E3_HIGH, L0_LOW, L1_LOW, G0_LOW, G1_LOW, G2_LOW, G3_LOW, E0_LOW, E1_LOW, 
      E2_LOW, E3_LOW, L0_INITIAL, L1_INITIAL, G0_INITIAL, G1_INITIAL, G2_INITIAL, 
      G3_INITIAL, E0_INITIAL, E1_INITIAL, E2_INITIAL, E3_INITIAL, L0_MODE, L1_MODE, 
      G0_MODE, G1_MODE, G2_MODE, G3_MODE, E0_MODE, E1_MODE, E2_MODE, E3_MODE, L0_PH,
      L1_PH, G0_PH, G1_PH, G2_PH, G3_PH, E0_PH, E1_PH, E2_PH, E3_PH, M_PH, L0_TIME_DELAY,
      L1_TIME_DELAY, G0_TIME_DELAY, G1_TIME_DELAY, G2_TIME_DELAY, G3_TIME_DELAY, 
      E0_TIME_DELAY, E1_TIME_DELAY, E2_TIME_DELAY, E3_TIME_DELAY, M_TIME_DELAY, 
      N_TIME_DELAY, EXTCLK3_COUNTER, EXTCLK2_COUNTER, EXTCLK1_COUNTER, EXTCLK0_COUNTER,
      CLK5_COUNTER, CLK4_COUNTER, CLK3_COUNTER, CLK2_COUNTER, CLK1_COUNTER, CLK0_COUNTER,
      ENABLE0_COUNTER, ENABLE1_COUNTER, CHARGE_PUMP_CURRENT, LOOP_FILTER_R, LOOP_FILTER_C,
      USE_VCO_BYPASS, USE_DC_COUPLING, RX_CLKOUT_RESOURCE, COMMON_RX_TX )
   RETURNS (clk[5..0], extclk[3..0], clkbad[1..0], activeclock, locked, clkloss, scandataout );


VHDL Component Declaration:

 
COMPONENT altpll
   GENERIC 
      (OPERATION_MODE            : STRING   := "NORMAL" ;
      PLL_TYPE                   : STRING   := "TYPE_AUTO" ;
      COMPENSATE_CLOCK           : STRING   := "CLK0" ;
      SCAN_CHAIN                 : STRING   := "LONG";
      PRIMARY_CLOCK              : STRING   := "INCLK0" ;
      INCLK0_INPUT_FREQUENCY     : POSITIVE ;
      INCLK1_INPUT_FREQUENCY     : NATURAL  := 1;
      GATE_LOCK_SIGNAL           : STRING   := "NO";
      GATE_LOCK_COUNTER          : INTEGER  := 1;
      LOCK_HIGH                  : NATURAL  := 1;
      LOCK_LOW                   : NATURAL  := 1;
      SWITCH_OVER_ON_LOSSCLK     : STRING   := "OFF" ;
      SWITCH_OVER_COUNTER        : NATURAL  := 0;
      ENABLE_SWITCH_OVER_COUNTER : STRING   := "OFF";
      FEEDBACK_SOURCE            : STRING   := "EXT_CLK0" ;
      BANDWIDTH                  : NATURAL  := 0;
      BANDWIDTH_TYPE             : STRING   := "UNUSED";
      SPREAD_FREQUENCY           : NATURAL  := 0;
      DOWN_SPREAD                : NATURAL  := 0;
      CLK5_MULTIPLY_BY           : POSITIVE := 1;
      CLK4_MULTIPLY_BY           : POSITIVE := 1;
      CLK3_MULTIPLY_BY           : POSITIVE := 1;
      CLK2_MULTIPLY_BY           : POSITIVE := 1;
      CLK1_MULTIPLY_BY           : POSITIVE := 1;
      CLK0_MULTIPLY_BY           : POSITIVE := 1;
      CLK5_DIVIDE_BY             : POSITIVE := 1;
      CLK4_DIVIDE_BY             : POSITIVE := 1;
      CLK3_DIVIDE_BY             : POSITIVE := 1;
      CLK2_DIVIDE_BY             : POSITIVE := 1;
      CLK1_DIVIDE_BY             : POSITIVE := 1;
      CLK0_DIVIDE_BY             : POSITIVE := 1;
      CLK5_PHASE_SHIFT           : NATURAL  := 0;
      CLK4_PHASE_SHIFT           : NATURAL  := 0;
      CLK3_PHASE_SHIFT           : NATURAL  := 0;
      CLK2_PHASE_SHIFT           : NATURAL  := 0;
      CLK1_PHASE_SHIFT           : NATURAL  := 0;
      CLK0_PHASE_SHIFT           : NATURAL  := 0;
      CLK5_TIME_DELAY            : STRING   := "0";
      CLK4_TIME_DELAY            : STRING   := "0";
      CLK3_TIME_DELAY            : STRING   := "0";
      CLK2_TIME_DELAY            : STRING   := "0";
      CLK1_TIME_DELAY            : STRING   := "0";
      CLK0_TIME_DELAY            : STRING   := "0";
      CLK5_DUTY_CYCLE            : NATURAL  := 50;
      CLK4_DUTY_CYCLE            : NATURAL  := 50;
      CLK3_DUTY_CYCLE            : NATURAL  := 50;
      CLK2_DUTY_CYCLE            : NATURAL  := 50;
      CLK1_DUTY_CYCLE            : NATURAL  := 50;
      CLK0_DUTY_CYCLE            : NATURAL  := 50;
      EXTCLK3_MULTIPLY_BY        : POSITIVE := 1;
      EXTCLK2_MULTIPLY_BY        : POSITIVE := 1;
      EXTCLK1_MULTIPLY_BY        : POSITIVE := 1;
      EXTCLK0_MULTIPLY_BY        : POSITIVE := 1;
      EXTCLK3_DIVIDE_BY          : POSITIVE := 1;
      EXTCLK2_DIVIDE_BY          : POSITIVE := 1;
      EXTCLK1_DIVIDE_BY          : POSITIVE := 1;
      EXTCLK0_DIVIDE_BY          : POSITIVE := 1;
      EXTCLK3_PHASE_SHIFT        : NATURAL  := 0;
      EXTCLK2_PHASE_SHIFT        : NATURAL  := 0;
      EXTCLK1_PHASE_SHIFT        : NATURAL  := 0;
      EXTCLK0_PHASE_SHIFT        : NATURAL  := 0;
      EXTCLK3_TIME_DELAY         : STRING   := "0";
      EXTCLK2_TIME_DELAY         : STRING   := "0";
      EXTCLK1_TIME_DELAY         : STRING   := "0";
      EXTCLK0_TIME_DELAY         : STRING   := "0";
      EXTCLK3_DUTY_CYCLE         : NATURAL  := 50;
      EXTCLK2_DUTY_CYCLE         : NATURAL  := 50;
      EXTCLK1_DUTY_CYCLE         : NATURAL  := 50;
      EXTCLK0_DUTY_CYCLE         : NATURAL  := 50;
      VCO_MIN                    : NATURAL  := 0;
      VCO_MAX                    : NATURAL  := 0;
      VCO_CENTER                 : NATURAL  := 0;
      PFD_MIN                    : NATURAL  := 0;
      PFD_MAX                    : NATURAL  := 0;
      M_INITIAL                  : NATURAL  := 1;
      M                          : NATURAL  := 0;
      N                          : NATURAL  := 1;
      M2                         : NATURAL  := 1;
      N2                         : NATURAL  := 1;
      SS                         : NATURAL  := 1;
      L0_HIGH                    : NATURAL  := 1;
      L1_HIGH                    : NATURAL  := 1;
      G0_HIGH                    : NATURAL  := 1;
      G1_HIGH                    : NATURAL  := 1;
      G2_HIGH                    : NATURAL  := 1;
      G3_HIGH                    : NATURAL  := 1;
      E0_HIGH                    : NATURAL  := 1;
      E1_HIGH                    : NATURAL  := 1;
      E2_HIGH                    : NATURAL  := 1;
      E3_HIGH                    : NATURAL  := 1;
      L0_LOW                     : NATURAL  := 1;
      L1_LOW                     : NATURAL  := 1;
      G0_LOW                     : NATURAL  := 1;
      G1_LOW                     : NATURAL  := 1;
      G2_LOW                     : NATURAL  := 1;
      G3_LOW                     : NATURAL  := 1;
      E0_LOW                     : NATURAL  := 1;
      E1_LOW                     : NATURAL  := 1;
      E2_LOW                     : NATURAL  := 1;
      E3_LOW                     : NATURAL  := 1;
      L0_INITIAL                 : NATURAL  := 1;
      L1_INITIAL                 : NATURAL  := 1;
      G0_INITIAL                 : NATURAL  := 1;
      G1_INITIAL                 : NATURAL  := 1;
      G2_INITIAL                 : NATURAL  := 1;
      G3_INITIAL                 : NATURAL  := 1;
      E0_INITIAL                 : NATURAL  := 1;
      E1_INITIAL                 : NATURAL  := 1;
      E2_INITIAL                 : NATURAL  := 1;
      E3_INITIAL                 : NATURAL  := 1;
      L0_MODE                    : STRING   := "BYPASS_MODE" ;
      L1_MODE                    : STRING   := "BYPASS_MODE" ;
      G0_MODE                    : STRING   := "BYPASS_MODE" ;
      G1_MODE                    : STRING   := "BYPASS_MODE" ;
      G2_MODE                    : STRING   := "BYPASS_MODE" ;
      G3_MODE                    : STRING   := "BYPASS_MODE" ;
      E0_MODE                    : STRING   := "BYPASS_MODE" ;
      E1_MODE                    : STRING   := "BYPASS_MODE" ;
      E2_MODE                    : STRING   := "BYPASS_MODE" ;
      E3_MODE                    : STRING   := "BYPASS_MODE" ;
      L0_PH                      : NATURAL  := 0;
      L1_PH                      : NATURAL  := 0;
      G0_PH                      : NATURAL  := 0;
      G1_PH                      : NATURAL  := 0;
      G2_PH                      : NATURAL  := 0;
      G3_PH                      : NATURAL  := 0;
      E0_PH                      : NATURAL  := 0;
      E1_PH                      : NATURAL  := 0;
      E2_PH                      : NATURAL  := 0;
      E3_PH                      : NATURAL  := 0;
      M_PH                       : NATURAL  := 0;
      L0_TIME_DELAY              : NATURAL  := 0;
      L1_TIME_DELAY              : NATURAL  := 0;
      G0_TIME_DELAY              : NATURAL  := 0;
      G1_TIME_DELAY              : NATURAL  := 0;
      G2_TIME_DELAY              : NATURAL  := 0;
      G3_TIME_DELAY              : NATURAL  := 0;
      E0_TIME_DELAY              : NATURAL  := 0;
      E1_TIME_DELAY              : NATURAL  := 0;
      E2_TIME_DELAY              : NATURAL  := 0;
      E3_TIME_DELAY              : NATURAL  := 0;
      M_TIME_DELAY               : NATURAL  := 0;
      N_TIME_DELAY               : NATURAL  := 0;
      EXTCLK3_COUNTER            : STRING   := "E3" ;
      EXTCLK2_COUNTER            : STRING   := "E2" ;
      EXTCLK1_COUNTER            : STRING   := "E1" ;
      EXTCLK0_COUNTER            : STRING   := "E0" ;
      CLK5_COUNTER               : STRING   := "G3" ;
      CLK4_COUNTER               : STRING   := "G2" ;
      CLK3_COUNTER               : STRING   := "G1" ;
      CLK2_COUNTER               : STRING   := "G0" ;
      CLK1_COUNTER               : STRING   := "L1" ;
      CLK0_COUNTER               : STRING   := "L0" ;
      ENABLE0_COUNTER            : STRING   := 
      ENABLE1_COUNTER            : STRING   := 
      CHARGE_PUMP_CURRENT        : NATURAL  := 2;
      LOOP_FILTER_R              : STRING   := "1.0";
      LOOP_FILTER_C              : NATURAL  := 5
      USE_VCO_BYPASS             : STRING   :=
      USE_DC_COUPLING            : STRING   :=
      RX_CLKOUT_RESOURCE         : STRING   :=);

   PORT (inclk                        : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
        fbin, pllena, scanclk,
           scandata                   : IN STD_LOGIC := '1';
        clkswitch, areset, pfdena,
           scanaclr                   : IN STD_LOGIC := '0';
        clkena                        : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '1');
        extclkena                     : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '1');
        clk                           : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
        extclk                        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        clkbad                        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
        activeclock, clkloss, locked
           scandataout                : OUT STD_LOGIC);

END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;


Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
inclk[] Yes The clock port that drives the PLL. The PRIMARY_CLOCK parameter specifies which clock the PLL uses. You can switch clocks with the clkswitch port. You can use the active_clock output port to specify if inclk1 or inclk2 port is used.
fbin No The external feedback input port for the PLL. The fbin port must be specified if the OPERATION_MODE parameter is set to EXTERNAL_FEEDBACK mode. To complete the feedback loop, there must be a board-level connection between the fbin pin and the external clock output pin of the PLL.
pllena No The PLL enable signal. When the pllena port is high, the PLL drives out a signal. When the pllena port is low, the PLL does not drive out a signal and goes out of lock. The pllena port acts as a combined enable and reset pin. When the pin is reasserted, the PLL has to re-lock. The device contains only one enable pin. If a PLL on the device uses the enable pin, all PLLs on the device must use the same enable pin.
clkswitch No Switches between input clock ports. The clkswitch port can only be connected if both the inclk0 and inclk1 ports are connected.
areset No Resets all counters to initial values. This port resets all counters, including the GATE_LOCK_COUNTER parameter, to their initial values. The PLL can be programmed after the device has been configured.
pfdena No Enables the phase frequency detector (PFD). Allows the VCO pin to continue to operate. When the PFD is disabled, the PLL continues to operate regardless of the input clock. Because the output clock frequency does not change for some time, you can use pfdena port as a shutdown or cleanup function when a reliable input clock is no longer available.
clkena[] No Enables the clk[] ports to the PLL.  
extclkena[] No Enables the extclk[] ports to the PLL.  
scanclk No Clock signal for the serial scan chain.  
scanaclr No Asynchronous clear for the real-time programming scan chain or the serial scan chain.  
scandata No Contains the data for the serial scan chain.  

OUTPUT PORTS

Port Name Required Description Comments
clk[] No The clock output of the PLL.  
extclk[] No The clock output that feeds the dedicated pins.  
clkbad[] No Specifies which signal goes high. If the inclk0 stops toggling, the clkbad0 is high. If the inclk1 stops toggling, the clkbad1 is high.
activeclock No Specifies which input clock port is used. When the activeclock port is high, clk0 port is used. When the activeclock port is low, clk1 port is used.
clkloss No Specifies when the clock switchover circuit initiates. The clock switchover circuit initiates when the primary reference clock is not toggling correctly or if you specify with the clkswitch input port.
locked No Gives the status of the PLL. When the PLL is locked, this signal is VCC. When the PLL is out of lock, this signal is GND. The locked port may pulse high and low while the PLL is in the process of achieving lock.
scandataout No The data output for the serial scan chain. You can use the scandataout output to determine when reconfiguration is complete. The last output bit is cleared when reconfiguration is finished.


Parameter Descriptions:
Parameter Type Required Comments
OPERATION_MODE String Yes Specifies the operation of the PLL. Values are "EXTERNAL_FEEDBACK", "NO_COMPENSATION", "NORMAL", and "ZERO_DELAY_BUFFER". If omitted, the default is NORMAL. In NORMAL mode, the PLL compensates for the delay of the internal clock network used by the clock output specified in the COMPENSATE_CLOCK parameter. If the PLL is also used to drive the internal clock network, a corresponding phase shift of that network results. In ZERO_DELAY_BUFFER mode, the PLL must feed an external clock output pin and compensate for the delay introduced by that pin. The signal observed on the pin will be synchronized to the input clock. If the PLL is also used to drive the internal clock network, a corresponding phase shift of that network results. In EXTERNAL_FEEDBACK mode, the fbin port must be connected to an input pin and there must be a board-level connection between this input pin and an external clock output pin, which is specified with FEEDBACK_SOURCE parameter. The fbin port is aligned with the input clock. In NO_COMPENSATION mode, the PLL does not align a clock to the input, which leads to better jitter performance.
PLL_TYPE String No Specifies the type of PLL to instantiate. Values are "AUTO", "ENHANCED", and "FAST". If omitted, the default is AUTO.
COMPENSATE_CLOCK String No Specifies the output clock port which should be compensated. If the OPERATION_MODE parameter is specified to NORMAL, values are "CLK[]", "GCLK[]", "LCLK[]", or "LVDSCLK[]". If the OPERATION_MODE parameter is specified to ZERO_DELAY_BUFFER, value is "EXTCLK[]". This clock cannot offset with respect to the reference clock, and this relationship is preserved closely even upon temperature and frequency changes. In NORMAL mode, default is CLK0. In ZERO_DELAY_BUFFER mode, default is EXTCLK0. For example, if CLK0 is specified when the OPERATION_MODE parameter is specified to NORMAL, the Compiler's compensation selection in terms of GCLK[], LCLK[], or LVDSCLK[] is based on CLK0 routing.
SCAN_CHAIN String No Specifies the length of the scan chain. Values are "LONG" or "SHORT". If omitted, the default is LONG. If "LONG" is specified, the scan chain length is 10 counters. If "SHORT" is specified, the scan chain length is 6 counters.
PRIMARY_CLOCK String No Specifies the primary reference clock of the PLL. Values are "INCLK0" or "INCLK1". If omitted, the default is INCLK0. You can use the clock switch scheme to switch between clocks; however, you can only switch back to the primary clock with a user initiated switch.
INCLK0_INPUT_FREQUENCY Integer Yes Specifies the input frequency for the inclk0 clock. The Compiler uses the frequency of clk0 port to calculate the PLL parameters, but also analyzes and reports the phase shifts for the clk1 port.
INCLK1_INPUT_FREQUENCY Integer No Specifies the input frequency for the inclk1 clock. The Compiler uses the frequency of clk0 port to calculate the PLL parameters, but also analyzes and reports the phase shifts for the clk1 port.
GATE_LOCK_SIGNAL String No Specifies if the locked port should be internally gated with a 20-bit programmable counter so it does not oscillate during initial power-up. Values are "NO" and "YES". If omitted, default is NO.
GATE_LOCK_COUNTER Integer No Specifies the value for the 20-bit counter that gates the locked output port before sending it to the locked port. This parameter is required for simulation with other EDA simulators.
LOCK_HIGH Integer No Specifies the number of half-clock cycles that the output clocks must be locked before the locked port goes high. This parameter is required for simulation with other EDA simulators.
LOCK_LOW Integer No Specifies the number of half-clock cycles that the output clocks must be out of lock before the locked port goes low. This parameter is required for simulation with other EDA simulators.
SWITCH_OVER_ON_LOSSCLK String No Specifies whether the loss of lock condition should initiate a clock switch over. Values are "ON" or "OFF". If omitted, the value is OFF.
SWITCH_OVER_COUNTER String No Specifies, in clock cycles after a switchover condition, when the input clock is switched. Values are "0" through "31". If omitted, the value is 0.
ENABLE_SWITCH_OVER_COUNTER String No Specifies whether to use the SWITCH_OVER_COUNTER parameter. Values are "ON" or "OFF". If omitted, the value is OFF.
FEEDBACK_SOURCE String No Specifies which clock output has a board-level connection to the fbin port. If the OPERATION_MODE parameter is specified to EXTERNAL_FEEDBACK, the FEEDBACK_SOURCE parameter is used. Values are "EXTCLK[]". If omitted, the value is EXTCLK0.
BANDWIDTH Integer No Specifies, in megahertz (MHz), bandwidth of the PLL. If this parameter is not specified, the Compiler automatically determines the value of the BANDWIDTH parameter to satisfy other PLL settings.
BANDWIDTH_TYPE String No Specifies the type of bandwidth for BANDWIDTH. Values are "AUTO", "CUSTOM", "HIGH", "LOW", or "MEDIUM". If omitted, default is AUTO.
SPREAD_FREQUENCY String No Specifies, in picoseconds (ps), the modulation frequency for spread spectrum.
DOWN_SPREAD String No Specifies the down spectrum percentage. Values range from 0 through 0.5.
CLK0_MULTIPLY_BY Integer No Specifies the integer multiplication factor, which must be greater than 0, for the clk0 port with respect to the input clock frequency. This parameter can be specified only if the clk0 port is used; however, it is not required if a Clock Settings assignment is specified for the clk0 port. If omitted, the default is 1.
CLK0_DIVIDE_BY Integer No Specifies the integer division factor, which must be greater than 0, for the clk0 port with respect to the input clock frequency. This parameter can be specified only if the clk0 port is used; however, it is not required if a Clock Settings assignment is specified for the clk0 port. If omitted, the default is 1.
CLK0_PHASE_SHIFT Integer No Specifies, in picoseconds (ps), phase shift for the clk0 port.
CLK0_TIME_DELAY String No Specifies, in picoseconds (ps), a delay value to be applied to the clk0 port. The CLK0_TIME_DELAY parameter affects only the clk0 port and is independent of the CLK0_PHASE_SHIFT parameter; therefore, the two port can be used simultaneously. If no units are specified, picoseconds (ps) are assumed. Legal values range from -3 ns through 6 ns in increments of 0.25 ns. These values should normally not be used as parameters except when reprogramming the PLL via the real-time programming interface.
CLK0_DUTY_CYCLE Integer No Specifies duty cycle for the clk0 port. If omitted, the default is 50.
CLK1_MULTIPLY_BY Integer No Specifies the integer multiplication factor, which must be greater than 0, for the clk1 port with respect to the input clock frequency. This parameter can be specified only if the clk1 port is used; however, it is not required if a Clock Settings assignment is specified for the clk1 port. If omitted, the default is 1.
CLK1_DIVIDE_BY Integer No Specifies the integer division factor, which must be greater than 0, for the clk1 port with respect to the input clock frequency. This parameter can be specified only if the clk1 port is used; however, it is not required if a Clock Settings assignment is specified for the clk1 port. If omitted, the default is 1.
CLK1_PHASE_SHIFT Integer No Specifies, in picoseconds (ps), phase shift for the clk1 port.
CLK1_TIME_DELAY String No Specifies, in picoseconds (ps), a delay value to be applied to the clk1 port. The CLK1_TIME_DELAY parameter affects only the clk1 port and is independent of the CLK1_PHASE_SHIFT parameter; therefore, the two port can be used simultaneously. If no units are specified, picoseconds (ps) are assumed. Legal values range from -3 ns through 6 ns in increments of 0.25 ns. These values should normally not be used as parameters except when reprogramming the PLL via the real-time programming interface.
CLK1_DUTY_CYCLE Integer No Specifies duty cycle for the clk1 port. If omitted, the default is 50.
CLK2_MULTIPLY_BY Integer No Specifies the integer multiplication factor, which must be greater than 0, for the clk2 port with respect to the input clock frequency. This parameter can be specified only if the clk2 port is used; however, it is not required if a Clock Settings assignment is specified for the clk2 port. If omitted, the default is 1.
CLK2_DIVIDE_BY Integer No Specifies the integer division factor, which must be greater than 0, for the clk2 port with respect to the input clock frequency. This parameter can be specified only if the clk2 port is used; however, it is not required if a Clock Settings assignment is specified for the clk2 port. If omitted, the default is 1.
CLK2_PHASE_SHIFT Integer No Specifies, in picoseconds (ps), phase shift for the clk2 port.
CLK2_TIME_DELAY String No Specifies, in picoseconds (ps), a delay value to be applied to the clk2 port. The CLK2_TIME_DELAY parameter affects only the clk2 port and is independent of the CLK2_PHASE_SHIFT parameter; therefore, the two port can be used simultaneously. If no units are specified, picoseconds (ps) are assumed. Legal values range from -3 ns through 6 ns in increments of 0.25 ns. These values should normally not be used as parameters except when reprogramming the PLL via the real-time programming interface.
CLK2_DUTY_CYCLE Integer No Specifies duty cycle for the clk2 port. If omitted, the default is 50.
CLK3_MULTIPLY_BY Integer No Specifies the integer multiplication factor, which must be greater than 0, for the clk3 port with respect to the input clock frequency. This parameter can be specified only if the clk3 port is used; however, it is not required if a Clock Settings assignment is specified for the clk03 port. If omitted, the default is 1.
CLK3_DIVIDE_BY Integer No Specifies the integer division factor, which must be greater than 0, for the clk3 port with respect to the input clock frequency. This parameter can be specified only if the clk3 port is used; however, it is not required if a Clock Settings assignment is specified for the clk3 port. If omitted, the default is 1.
CLK3_PHASE_SHIFT Integer No Specifies, in picoseconds (ps), phase shift for the clk3 port.
CLK3_TIME_DELAY String No Specifies, in picoseconds (ps), a delay value to be applied to the clk3 port. The CLK3_TIME_DELAY parameter affects only the clk3 port and is independent of the CLK3_PHASE_SHIFT parameter; therefore, the two port can be used simultaneously. If no units are specified, picoseconds (ps) are assumed. Legal values range from -3 ns through 6 ns in increments of 0.25 ns. These values should normally not be used as parameters except when reprogramming the PLL via the real-time programming interface.
CLK3_DUTY_CYCLE Integer No Specifies duty cycle for the clk3 port. If omitted, the default is 50.
CLK4_MULTIPLY_BY Integer No Specifies the integer multiplication factor, which must be greater than 0, for the clk4 port with respect to the input clock frequency. This parameter can be specified only if the clk4 port is used; however, it is not required if a Clock Settings assignment is specified for the clk4 port. If omitted, the default is 1.
CLK4_DIVIDE_BY Integer No Specifies the integer division factor, which must be greater than 0, for the clk4 port with respect to the input clock frequency. This parameter can be specified only if the clk4 port is used; however, it is not required if a Clock Settings assignment is specified for the clk4 port. If omitted, the default is 1.
CLK4_PHASE_SHIFT Integer No Specifies, in picoseconds (ps), phase shift for the clk4 port.
CLK4_TIME_DELAY String No Specifies, in picoseconds (ps), a delay value to be applied to the clk4 port. The CLK4_TIME_DELAY parameter affects only the clk4 port and is independent of the CLK4_PHASE_SHIFT parameter; therefore, the two port can be used simultaneously. If no units are specified, picoseconds (ps) are assumed. Legal values range from -3 ns through 6 ns in increments of 0.25 ns. These values should normally not be used as parameters except when reprogramming the PLL via the real-time programming interface.
CLK4_DUTY_CYCLE Integer No Specifies duty cycle for the clk4 port. If omitted, the default is 50.
CLK5_MULTIPLY_BY Integer No Specifies the integer multiplication factor, which must be greater than 0, for the clk5 port with respect to the input clock frequency. This parameter can be specified only if the clk5 port is used; however, it is not required if a Clock Settings assignment is specified for the clk5 port. If omitted, the default is 1.
CLK5_DIVIDE_BY Integer No Specifies the integer division factor, which must be greater than 0, for the clk5 port with respect to the input clock frequency. This parameter can be specified only if the clk5 port is used; however, it is not required if a Clock Settings assignment is specified for the clk5 port. If omitted, the default is 1.
CLK5_PHASE_SHIFT Integer No Specifies, in picoseconds (ps), phase shift for the clk5 port.
CLK5_TIME_DELAY String No Specifies, in picoseconds (ps), a delay value to be applied to the clk5 port. The CLK5_TIME_DELAY parameter affects only the clk5 port and is independent of the CLK5_PHASE_SHIFT parameter; therefore, the two port can be used simultaneously. If no units are specified, picoseconds (ps) are assumed. Legal values range from -3 ns through 6 ns in increments of 0.25 ns. These values should normally not be used as parameters except when reprogramming the PLL via the real-time programming interface.
CLK5_DUTY_CYCLE Integer No Specifies duty cycle for the clk5 port. If omitted, the default is 50.
EXTCLK0_MULTIPLY_BY Integer No Specifies the integer multiplication factor, which must be greater than 0 for the extclk0 port with respect to the input clock frequency. This parameter can only be specified if the extclk0 port is used; however, it is not required if a Clock Settings assignment is specified for the extclk0 port. If omitted, the default is 1.
EXTCLK0_DIVIDE_BY Integer No Specifies the integer division factor, which must be greater than 0 for the extclk0 port with respect to the input clock frequency. This parameter can only be specified if the extclk0 port is used; however, it is not required if a Clock Settings assignment is specified for the extclk0 port. If omitted, the default is 1.
EXTCLK0_PHASE_SHIFT Integer No Specifies the phase shift for the extclk0 port.
EXTCLK0_TIME_DELAY String No Specifies, in picoseconds (ps), a delay value to be applied to the exctclk0 port. The EXTCLK0_TIME_DELAY parameter affects only the exctclk0 port and is independent of the EXTCLK0_PHASE_SHIFT parameter; therefore, the two port can be used simultaneously. If no units are specified, picoseconds (ps) are assumed. Legal values range from -3 ns through 6 ns in increments of 0.25 ns. These values should normally not be used as parameters except when reprogramming the PLL via the real-time programming interface.
EXTCLK0_DUTY_CYCLE Integer No Specifies the duty cycle for the extclk0 port. If omitted, the default is 50.
EXTCLK1_MULTIPLY_BY Integer No Specifies the integer multiplication factor, which must be greater than 0 for the extclk1 port with respect to the input clock frequency. This parameter can only be specified if the extclk1 port is used; however, it is not required if a Clock Settings assignment is specified for the extclk1 port. If omitted, the default is 1.
EXTCLK1_DIVIDE_BY Integer No Specifies the integer division factor, which must be greater than 0 for the extclk1 port with respect to the input clock frequency. This parameter can only be specified if the extclk1 port is used; however, it is not required if a Clock Settings assignment is specified for the extclk0 port. If omitted, the default is 1.
EXTCLK1_PHASE_SHIFT Integer No Specifies the phase shift for the extclk1 port.
EXTCLK1_TIME_DELAY String No Specifies, in picoseconds (ps), a delay value to be applied to the exctclk1 port. The EXTCLK0_TIME_DELAY parameter affects only the exctclk1 port and is independent of the EXTCLK1_PHASE_SHIFT parameter; therefore, the two port can be used simultaneously. If no units are specified, picoseconds (ps) are assumed. Legal values range from -3 ns through 6 ns in increments of 0.25 ns. These values should normally not be used as parameters except when reprogramming the PLL via the real-time programming interface.
EXTCLK1_DUTY_CYCLE Integer No Specifies the duty cycle for the extclk1 port. If omitted, the default is 50.
EXTCLK2_MULTIPLY_BY Integer No Specifies the integer multiplication factor, which must be greater than 0 for the extclk2 port with respect to the input clock frequency. This parameter can only be specified if the extclk2 port is used; however, it is not required if a Clock Settings assignment is specified for the extclk2 port. If omitted, the default is 1.
EXTCLK2_DIVIDE_BY Integer No Specifies the integer division factor, which must be greater than 0 for the extclk2 port with respect to the input clock frequency. This parameter can only be specified if the extclk2 port is used; however, it is not required if a Clock Settings assignment is specified for the extclk0 port. If omitted, the default is 1.
EXTCLK2_PHASE_SHIFT Integer No Specifies the phase shift for the extclk2 port.
EXTCLK2_TIME_DELAY String No Specifies, in picoseconds (ps), a delay value to be applied to the exctclk2 port. The EXTCLK2_TIME_DELAY parameter affects only the exctclk2 port and is independent of the EXTCLK2_PHASE_SHIFT parameter; therefore, the two port can be used simultaneously. If no units are specified, picoseconds (ps) are assumed. Legal values range from -3 ns through 6 ns in increments of 0.25 ns. These values should normally not be used as parameters except when reprogramming the PLL via the real-time programming interface.
EXTCLK2_DUTY_CYCLE Integer No Specifies the duty cycle for the extclk2 port. If omitted, the default is 50.
EXTCLK3_MULTIPLY_BY Integer No Specifies the integer multiplication factor, which must be greater than 0 for the extclk3 port with respect to the input clock frequency. This parameter can only be specified if the extclk3 port is used; however, it is not required if a Clock Settings assignment is specified for the extclk3 port. If omitted, the default is 1.
EXTCLK3_DIVIDE_BY Integer No Specifies the integer division factor, which must be greater than 0 for the extclk3 port with respect to the input clock frequency. This parameter can only be specified if the extclk3 port is used; however, it is not required if a Clock Settings assignment is specified for the extclk0 port. If omitted, the default is 1.
EXTCLK3_PHASE_SHIFT Integer No Specifies the phase shift for the extclk3 port.
EXTCLK3_TIME_DELAY String No Specifies, in picoseconds (ps), a delay value to be applied to the exctclk3 port. The EXTCLK3_TIME_DELAY parameter affects only the exctclk3 port and is independent of the EXTCLK3_PHASE_SHIFT parameter; therefore, the two port can be used simultaneously. If no units are specified, picoseconds (ps) are assumed. Legal values range from -3 ns through 6 ns in increments of 0.25 ns. These values should normally not be used as parameters except when reprogramming the PLL via the real-time programming interface.
EXTCLK3_DUTY_CYCLE Integer No Specifies the duty cycle for the extclk3 port. If omitted, the default is 50.
VCO_MIN Integer No Specifies the minimum value for the VCO pin.
VCO_MAX Integer No Specifies the maximum value for the VCO pin.
VCO_CENTER Integer No Specifies the center value for the VCO pin.
PFD_MIN Integer No Specifies the minimum value for the PFD pin.
PFD_MAX Integer No Specifies the maximum value for the PFD pin.
M_INITIAL Integer No Specifies the initial value for the M counter. Provides direct access to the internal PLL parameters. If the M_INITIAL parameter is specified, all advanced parameters must be used. Values range from 1 through 512.
M Integer No Specifies the modulus for the M counter. Provides direct access to the internal PLL parameters. If the M parameter is specified, all advanced parameters must be used. Values range from 1 through 512.
N Integer No Specifies the modulus for the N counter. Provides direct access to the internal PLL parameters. If the N parameter is specified, all advanced parameters must be used. Values range from 1 through 512.
M2 Integer No Specifies the spread spectrum modulus for the M counter. Provides direct access to the internal PLL parameters. If the M2 parameter is specified, all advanced parameters must be used. Values range from 1 through 512.
N2 Integer No Specifies the spread spectrum modulus for the N counter. Provides direct access to the internal PLL parameters. If the N2 parameter is specified, all advanced parameters must be used. Values range from 1 through 512.
SS Integer No Specifies the modulus for the spread spectrum counter. Provides direct access to the internal PLL parameters. If the SS parameter is specified, all advanced parameters must be used. Values range from 1 through 32768.
E0_HIGH Integer No Specifies the high period count for the E0_HIGH counter. Values range from 1 through 512. If omitted, the default is 1.
E0_LOW Integer No Specifies the low period count for the E0_LOW counter. Values range from 1 through 512. If omitted, the default is 1.
E0_INITIAL Integer No Specifies the initial value for the E0_INITIAL counter. Values range from 1 through 512. If omitted, the default is 1.
E0_MODE String No Specifies the mode for the E0_MODE counter. Values are "BYPASS", "ODD", or "EVEN". If omitted, the default is BYPASS.
E0_PH Integer No Specifies the phase tap for the E0_PH counter. Values range from 0 through 7. If omitted, the default is 0.
E0_TIME_DELAY Integer No Specifies, in nanoseconds (ns), the time delay for the E0_TIME_DELAY counter. Values range from 0 ns through 3 ns. If omitted, the default is 0.
E1_HIGH Integer No Specifies the high period count for the E1_HIGH counter. Values range from 1 through 512. If omitted, the default is 1.
E1_LOW Integer No Specifies the low period count for the E1_LOW counter. Values range from 1 through 512. If omitted, the default is 1.
E1_INITIAL Integer No Specifies the initial value for the E1_INITIAL counter. Values range from 1 through 512. If omitted, the default is 1.
E1_MODE String No Specifies the mode for the E1_MODE counter. Values are "BYPASS", "ODD", or "EVEN". If omitted, the default is BYPASS.
E1_PH Integer No Specifies the phase tap for the E1_PH counter. Values range from 0 through 7. If omitted, the default is 0.
E1_TIME_DELAY Integer No Specifies, in nanoseconds (ns), the time delay for the E1_TIME_DELAY counter. Values range from 0 ns through 3 ns. If omitted, the default is 0.
E2_HIGH Integer No Specifies the high period count for the E2_HIGH counter. Values range from 1 through 512. If omitted, the default is 1.
E2_LOW Integer No Specifies the low period count for the E2_LOW counter. Values range from 1 through 512. If omitted, the default is 1.
E2_INITIAL Integer No Specifies the initial value for the E2_INITIAL counter. Values range from 1 through 512. If omitted, the default is 1.
E2_MODE String No Specifies the mode for the E2_MODE counter. Values are "BYPASS", "ODD", or "EVEN". If omitted, the default is BYPASS.
E2_PH Integer No Specifies the phase tap for the E2_PH counter. Values range from 0 through 7. If omitted, the default is 0.
E2_TIME_DELAY Integer No Specifies, in nanoseconds (ns), the time delay for the E2_TIME_DELAY counter. Values range from 0 ns through 3 ns. If omitted, the default is 0.
E3_HIGH Integer No Specifies the high period count for the E3_HIGH counter. Values range from 1 through 512. If omitted, the default is 1.
E3_LOW Integer No Specifies the low period count for the E3_LOW counter. Values range from 1 through 512. If omitted, the default is 1.
E3_INITIAL Integer No Specifies the initial value for the E3_INITIAL counter. Values range from 1 through 512. If omitted, the default is 1.
E3_MODE String No Specifies the mode for the E3_MODE counter. Values are "BYPASS", "ODD", or "EVEN". If omitted, the default is BYPASS.
E3_PH Integer No Specifies the phase tap for the E3_PH counter. Values range from 0 through 7. If omitted, the default is 0.
E3_TIME_DELAY Integer No Specifies, in nanoseconds (ns), the time delay for the E3_TIME_DELAY counter. Values range from 0 ns through 3 ns. If omitted, the default is 0.
G0_HIGH Integer No Specifies the high period count for the G0_HIGH counter. Values range from 1 through 512. If omitted, the default is 1.
G0_LOW Integer No Specifies the low period count for the G0_LOW counter. Values range from 1 through 512. If omitted, the default is 1.
G0_INITIAL Integer No Specifies the initial value for the G0_INITIAL counter. Values range from 1 through 512. If omitted, the default is 1.
G0_MODE String No Specifies the mode for the G0_MODE counter. Values are "BYPASS", "ODD", or "EVEN". If omitted, the default is BYPASS.
G0_PH Integer No Specifies the phase tap for the G0_PH counter. Values range from 0 through 7. If omitted, the default is 0.
G0_TIME_DELAY Integer No Specifies, in nanoseconds (ns), the time delay for the G0_TIME_DELAY counter. Values range from 0 ns through 3 ns. If omitted, the default is 0.
G1_HIGH Integer No Specifies the high period count for the G1_HIGH counter. Values range from 1 through 512. If omitted, the default is 1.
G1_LOW Integer No Specifies the low period count for the G1_LOW counter. Values range from 1 through 512. If omitted, the default is 1.
G1_INITIAL Integer No Specifies the initial value for the G1_INITIAL counter. Values range from 1 through 512. If omitted, the default is 1.
G1_MODE String No Specifies the mode for the G1_MODE counter. Values are "BYPASS", "ODD", or "EVEN". If omitted, the default is BYPASS.
G1_PH Integer No Specifies the phase tap for the G1_PH counter. Values range from 0 through 7. If omitted, the default is 0.
G1_TIME_DELAY Integer No Specifies, in nanoseconds (ns), the time delay for the G1_TIME_DELAY counter. Values range from 0 ns through 3 ns. If omitted, the default is 0.
G2_HIGH Integer No Specifies high period count for G2_HIGH counter. Values range from 1 through 512. If omitted, the default is 1.
G2_LOW Integer No Specifies the low period count for the G2_LOW counter. Values range from 1 through 512. If omitted, the default is 1.
G2_INITIAL Integer No Specifies the initial value for the G2_INITIAL counter. Values range from 1 through 512. If omitted, the default is 1.
G2_MODE String No Specifies the mode for the G2_MODE counter. Values are "BYPASS", "ODD", or "EVEN". If omitted, the default is BYPASS.
G2_PH Integer No Specifies the phase tap for the G2_PH counter. Values range from 0 through 7. If omitted, the default is 0.
G2_TIME_DELAY Integer No Specifies, in nanoseconds (ns), the time delay for the G2_TIME_DELAY counter. Values range from 0 ns through 3 ns. If omitted, the default is 0.
G3_HIGH Integer No Specifies the high period count for the G3_HIGH counter. Values range from 1 through 512. If omitted, the default is 1.
G3_LOW Integer No Specifies the low period count for the E0_LOW counter. Values range from 1 through 512. If omitted, the default is 1.
G3_INITIAL Integer No Specifies the initial value for the G3_INITIAL counter. Values range from 1 through 512. If omitted, the default is 1.
G3_MODE String No Specifies the mode for the G3_MODE counter. Values are "BYPASS", "ODD", or "EVEN". If omitted, the default is BYPASS.
G3_PH Integer No Specifies the phase tap for the G3_PH counter. Values range from 0 through 7. If omitted, the default is 0.
G3_TIME_DELAY Integer No Specifies, in nanoseconds (ns), the time delay for the G3_TIME_DELAY counter. Values range from 0 ns through 3 ns. If omitted, the default is 0.
L0_HIGH Integer No Specifies the high period count for the L0_HIGH counter. Values range from 1 through 512. If omitted, the default is 1.
L0_LOW Integer No Specifies the low period count for the L0_LOW counter. Values range from 1 through 512. If omitted, the default is 1.
L0_INITIAL Integer No Specifies the initial value for the L0_INITIAL counter. Values range from 1 through 512. If omitted, the default is 1.
L0_MODE String No Specifies the mode for the L0_MODE counter. Values are "BYPASS", "ODD", or "EVEN". If omitted, the default is BYPASS.
L0_PH Integer No Specifies the phase tap for the L0_PH counter. Values range from 0 through 7. If omitted, the default is 0.
L0_TIME_DELAY Integer No Specifies, in nanoseconds (ns), the time delay for the L0_TIME_DELAY counter. Values range from 0 ns through 3 ns. If omitted, the default is 0.
L1_HIGH Integer No Specifies the high period count for the L1_HIGH counter. Values range from 1 through 512. If omitted, the default is 1.
L1_LOW Integer No Specifies the low period count for the L1_LOW counter. Values range from 1 through 512. If omitted, the default is 1.
L1_INITIAL Integer No Specifies the initial value for the L1_INITIAL counter. Values range from 1 through 512. If omitted, the default is 1.
L1_MODE String No Specifies the mode for the L1_MODE counter. Values are "BYPASS", "ODD", or "EVEN". If omitted, the default is BYPASS.
L1_PH Integer No Specifies the phase tap for the L1_PH counter. Values range from 0 through 7. If omitted, the default is 0.
L1_TIME_DELAY Integer No Specifies, in nanoseconds (ns), the time delay for the L1_TIME_DELAY counter. Values range from 0 ns through 3 ns. If omitted, the default is 0.
EXTCLK0_COUNTER String No Specifies the counter for the extclk0 port. Values are "E0", "E1", "E2", or "E3". If omitted, the default is E0.
EXTCLK1_COUNTER String No Specifies the counter for the extclk1 port. Values are "E0", "E1", "E2", or "E3". If omitted, the default is E1.
EXTCLK2_COUNTER String No Specifies the counter for the extclk2 port. Values are "E0", "E1", "E2", or "E3". If omitted, the default is E2.
EXTCLK3_COUNTER String No Specifies the counter for the extclk3 port. Values are "E0", "E1", "E2", or "E3". If omitted, the default is E3.
CLK0_COUNTER String No Specifies the counter for the clk0 port. Values are "G0", "G1", "G2", "G3", "L0", or "L1". If omitted, the default is L0.
CLK1_COUNTER String No Specifies the counter for the clk1 port. Values are "G0", "G1", "G2", "G3", "L0", or "L1". If omitted, the default is L1.
CLK2_COUNTER String No Specifies the counter for the clk2 port. Values are "G0", "G1", "G2", "G3", "L0", or "L1". If omitted, the default is G0.
CLK3_COUNTER String No Specifies the counter for the clk3 port. Values are "G0", "G1", "G2", "G3", "L0", or "L1". If omitted, the default is G1.
CLK4_COUNTER String No Specifies the counter for the clk4 port. Values are "G0", "G1", "G2", "G3", "L0", or "L1". If omitted, the default is G2.
CLK5_COUNTER String No Specifies the counter for the clk5 port. Values are "G0", "G1", "G2", "G3", "L0", or "L1". If omitted, the default is G3.
ENABLE0_COUNTER String No Specifies the counter for the enable0 port. Values are "L0" or "L1".
ENABLE1_COUNTER String No Specifies the counter for the enable1 port. Values are "L0" or "L1".
CHARGE_PUMP_CURRENT Integer No Specifies, in microamperes (μA), the value of the charge pump current. Values range from 2 μA through 205 μA. If omitted, the default is 2.
LOOP_FILTER_R String No Specifies, in kilohms (KΩ), the value of the loop resistor. Values range from 1 KΩ through 20 KΩ. The Compiler cannot achieve all values.
LOOP_FILTER_C Integer No Specifies, in picofarads (pF), the value of the loop capacitor. Values range from 5 pF through 20 pF. The Compiler cannot achieve all values.


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