AHDL

Using Iteratively Generated Logic



When you wish to use multiple blocks of logic that are very similar, you can use the For Generate Statement to iteratively generate logic based on a numeric range delimited by arithmetic expressions.

The iter_add.tdf file shown below shows an example of iterative logic generation:

CONSTANT NUM_OF_ADDERS = 8;

SUBDESIGN iter_add
(
   a[NUM_OF_ADDERS..1], b[NUM_OF_ADDERS..1], cin : INPUT;
   c[NUM_OF_ADDERS..1], cout                     : OUTPUT;
)

VARIABLE
   sum[NUM_OF_ADDERS..1], carryout[(NUM_OF_ADDERS+1)..1] : NODE;

BEGIN
   carryout[1] = cin;
   FOR i IN 1 TO NUM_OF_ADDERS GENERATE
      sum[i] = a[i] $ b[i] $ carryout[i];   % Full Adder %
      carryout[i+1] = a[i] & b[i] # carryout[i] & (a[i] $ b[i]);
   END GENERATE;
   cout = carryout[NUM_OF_ADDERS+1];
   c[] = sum[];
END;

In iter_add.tdf, the For Generate Statement is used to instantiate full adders that each perform one bit of the NUM_OF_ADDERS-bit (that is, 8-bit) addition. The carryout of each bit is generated along with each full adder.

NOTE The If Generate Statement is especially useful with For Generate Statements that handle special cases differently, for example, the first and last stages of a multiple stage multiplier. See Using Conditionally Generated Logic for more information.


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