(C) Yann Guidon 2001 (whygee@f-cpu.org) | slide 1 / 18
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Subject of this presentation :
"Instruction scheduling and the memory interface of the FC0"

## Disclaimers :

- This is a technical (not marketing) overview of some major characteristics of the F-CPU design philosophy and the implementation in the FC0.
- It presents the backgrounds and design choices of an ongoing (unfinished) work.
- Not all the details are presented here ! RTFM @ http://www.f-cpu.seul.org/manual

Foreword :

At first, the FC0 is a curious mix between a classical MIPS/DLX pipeline (see P&H's books) and a CDC6600 (see the excellent description in G. Bell's book "Computer Structures : Readings and Examples", now readable online). However, the ambition to surpass the early ALPHA architecture and the strong will to avoid any issue of any kind with protection or fault handling, led to design a very particular architecture. It is heavily based on speculative flags, "split" instructions and other unseen quirks. And it all looks like a "classical RISC" to the newcomers ...