| Projects F-CPU F-Mainboard F-Tools Communication Mailing lists IRC Forum Administrative Groups & Teams Voting List Misc Design Manual Developement Principles FAQ Old Arch Original website | # Tools and Documentation ## Tools We will put here a list of tools that are/seem interesting for the project. They should be free to use, and uncrippled (no demo version of commercial tools). There is an interesting part on this page suggesting that Verilog and VHDL are complementary. "VHDL and Verilog are more complimentary than overlapping, the former is suited to top-down design and the latter to bottom-up implementation." #### Verilog VBS: Free copy-lefted Verilog simulator called "vbs", written by Jimen Ching and Lay Hoon Tho. V2000 The aim of the V2000 project is implement a Verilog-AMS (and VHDL) simulator system. #### VHDL Alliance The Alliance CAD system (Uiversite de Paris) includes a VHDL simulator and a lot of other tools. However, only a very small subset of VHDL is supported. FreeHDL A project to develop a free, open source, GPL'ed VHDL (VHDL-93 compliant) simulator for Linux of commercial quality with graphical waveform viewer and source level debugger. Some of the parser, simulator and tool code is already available. ivsim A free VHDL simulator from Korea! ## Documentation The most referenced book has been: "Computer Architecture: a Quantitative Approach" by David A. Patterson, John L. Hennessy, David Goldberg published by Morgan Kaufman Publishers. ISBN: 1558603298 Last modified: Sun Mar 14 02:09:11 CET 1999