(C) Yann Guidon 2001 (whygee@f-cpu.org) | slide 4 / 18
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Starting point of the FC0 : Clock speed issue

Technology handicap ---> "carpaccio" CPU

- Faster clock -> shorter Critical DataPath -> 6x 4-input gates in the CDP (This goal is here to emphasize on the simplicity of the pipeline stages, it's not a "golden rule" because a lot of other parameters must be also considered)
- This "granularity" maps well in most digital technologies : ASIC, FPGA, Sea of gates or Full Custom... It is not too specifically targeted at one technology and the porting effort is minimized.
- Stage is deep enough to perform a 8-bit add/sub or a 64-bit increment.
- When a unit becomes too complex, it must be split.
- CDP determined from the start :
  - no "hidden CDP" that slows the clock down in the middle of the project
  - very simple and easy design of the units (fortunately because everything must be redesigned)
  - emphasis on short stage pipelining for every part of the project favours "matched" and balanced pipeline stage design.
  - the number of pipeline stages is not the issue.