(C) Yann Guidon 2001 (whygee@f-cpu.org) | slide 11 / 18
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Memory protection

All the pointers are available from the Xbar and checked by a TLB
that translates the task's logical address into a physical address.

- TLB entries are SW-replaced through Special Registers with the help of LRU HW
- 4 page sizes : 4KB, 32KB, 256KB and 2MB, plus probably a set of "fence registers" for larger pages.
- TLB entries contain cachability informations, access rights (R/W/RW/X), access counter and subdomain usage counters, VMID tag ...