(C) Yann Guidon 2001 (whygee@f-cpu.org) | slide 10 / 18
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Scheduling of one instruction (3)
Allocation of the Xbar slots with a FIFO

- The opcode and the flags of the current instruction are the inputs of a hardwired lookup table. The output indicates how many slots are required (1 or 2 write buses ?) and how many cycles are required for the completion of the operation.
- When the operation is issued (if no hazard on the scoreboard and the FIFO is detected), the selected slot is filled with the number of the register that must be written to.
- When the FIFO shifts down, the number reaches the bottom and commands the control wires of the Xbar and the Register Set.
- The depth of the FIFO is 8 cycles. It corresponds to the highest latency of the execution units (IMU: 6 cycles) plus the 2 x Xbar cycles.
- An additional down-counter extends the FIFO for the long and high-latency divide unit (not pipelined version). When the counter is elapsed, the behaviour is normal for the rest of the FIFO (the register number is injected on the top of the FIFO).
- Load instructions are stalled when the data is not present in the LSU's buffer.