(C) Yann Guidon 2001 (whygee@f-cpu.org) | slide 17 / 18
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Evolution of the F-CPU

- explicit register renaming -> more usable registers
- Possible directions :
  - SMT (Simultaneous Multi Threading),
  - multi-core chips
  - RISC->TTA translator
  - eDRAM (embedded DRAM)
  - F-BUS, ...
- New instructions : Scatter-Gather, Permute ...
- F-CPU II ?