version : july 10th, 2001 :
The F-CPU "official" (but not yet working) bundle
is now in cvs at gaos.org. You can either extract
the tree with CVS or download branches or the full
bundle at http://f-cpu.gaos.org (it's a weekly tar).

Unfortunately, the project has not much been enhanced
since the last 7 months.


F-CPU project, nov. 29th 2000 :
some sparse UNIX stuffs and cleaning...
the directory names must be changed in all the scripts !
EU_SR is still unfinished. filenames and
formattings are not consistent, some are
UNIX and other DOS ... PKZIP has removed the
upcase characters (or was it UNZIP ?) so i
stick to the lower cases, except for the text files...


F-CPU project, nov. 26th 2000 :
release of yet another package !
bundled by whygee@f-cpu.org


Last time, the checkings were incomplete
so it remained an unofficial release.
Michael has added a wrapper for iadd.vhdl
and Erik Hansen has written a INC unit.
I have restored the full gate library
and added a CHARTER.txt file. I also
completely re-reorganised the directories.
I still have to rewrite the ROP2 and INC
units. It's not easy because i only have
a few hours per week-end to do this...



F-CPU project, nov. 17th 2000 :
release of the second package !
bundled by whygee@f-cpu.org


Although my new work at Meta Systems/Mentor Graphics
is taking me 200% of my time, i have finally managed to
output this updated bundle. Beware, it might still contain
inacuracies despite our continuous efforts. Inacuracies are
not as severe as incompleteness, though :-/

This package contains additions and modifications
from Michael Riepe, Erik Hansen and Yann Guidon.

Erik has checked the portability of the package under
Modelsim 5.3XE starter and Modelsim 5.4c.

Erik wrote :
"
There where some changes to be made to the ROP2_testbench.vhdl file.

1. The write Commands needed a little change:

   old: write (lout, "* cycle # : ");
   new: write (lout, string'("* cylcle # : "));

   It seems as if Modelsim made a Typecast do std_logic_vector, so
   I made the explicit typecast to string.

2. function get_hexa uses variables which are normally out of
   scope for pure functions ( although they are declared as
   being shared ). So I made get_hexa an impure function.

   old: function get_hexa(...
   new: impure function get_hexa(...

I've attached the changed file, together with compile script for
Windows/Modelsim5.3XE Starter (testrop2.bat)  
and Solaris/Modelsim5.4c (testrop2.unix). Should work with outer
Version of Modelsim as well;-)   
"

Michael has added a wonderful ASU (SIMD/Saturated integer Add/Sub Unit)
that can be split in 2 stages of 6 gates of depths each.
He uses a library of elementary gates that ease the synthesis and the portability
of the unit. After reading his work, i think i should rewrite the ROP2
unit so it matches the style and quality of the IADD unit. Counting the gates
all the time might seem a bit masochist but it helps a lot to keep the
design size reasonable. Even if a stage doesn't match the targeted 6-gates
depth, at least it helps to identify the critical datapaths that must be either
reduced or split.

Micheal wrote :
"
Second turn...

I changed the adder from carry-select to carry-increment after I figured
out how to do the SIMD thing without increasing the delay... took me
a while.  I also added limited 8-bit support -- add/addc/sub/subb now
takes 1 cycle (6 gates), but saturated mode (adds/subf) needs the whole
pipeline (2 cycles).  There is also a reasonably complex test suite now;
it doesn't check everything, but IMHO it's sufficient.  Of course, the
unit passes the test.  (BTW: Vanilla VHDL finally reached its limits --
it dies with an `opcode botch' error, whatever that means -- but Simili
still works fine).

I threw out the MUXes (not needed) and the more complex components
(there were to many special cases); according to vhdle.exe, there are
now 1268 components, and all of them are standard gates (I'll insert
the pipeline register later).

I think I'll let you play with this unit for a while and concentrate on
the multiplier again.
"


On top of that, i have added some more Special Registers to f-cpu_config.vhdl :
SR_URL, SR_IRQ_BASE, SR_IRQ_SIZE, SR_TRAP_BASE, SR_TRAP_SIZE, SR_SYSCALL_BASE,
SR_SYSCALL_SIZE, others will certainly appear soon.


I have reorganised the files in different subdirectories. This disturbs
a bit some early testbenches, and i have not made scritps that compile
and test all the units. Lack of time...


We must remark that the architectures are not yet precisely managed.
In the future, we must define a coherent and homogenised naming procedure
for the architectures.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

F-CPU project, oct. 26th 2000 :
release of the first package !
bundled by whygee@f-cpu.org

Hi,

It was finally time to release a first bundle of
VHDL files. It is not a complete set of files
because we have just started :-) The other design
files will be rather slow to come, too, because of
the necessity to check all the functionalities.
On top of that, we're not much people working on
this side of the project and we can't spend our
whole days designing the F-CPU. Finally the
toolsuite is still a problem : the provided files
have not been synthesized.

At least, this package shows the current status of
the project. It also serves as a basis for future
design files and it constitutes a part of the global
F-CPU and FC0 specification. It will be used to
update the F-CPU manual v0.2.


Some details :
- all the files are distributed under the GPL.
- they have been compiled and simulated with Simili
  from Symphony EDA. No synthesis has been attempted
  yet.
- the design and the specifications are thought to
  be as accurate as possible. though, as you can
  imagine, the implementation reveals some
  inacuracies in the F-CPU manual. These files are
  based on the (old) F-CPU manual v0.2 that should
  be now updated.


The files : the names are explicit but here is an
overview.

   ############ Main design files : ############

* ROP2.vhdl : the design file itself, it defines the
  ROP2 unit as defined in the F-CPU manual (v0.2).
  It is rather simple, but has the merit that it
  exists :-)

* F-CPU_config.vhdl : the configuration file.
  It defines a lot of the main F-CPU and FC0
  characteristics, mainly the word size. This
  file/package MUST be reused by every F-CPU
  design.

     ############ Testbench : ############

* ROP2_testbench.vhdl : the testbench. It contains
  a little interpreter that reads a vector file
  and feeds a ROP2 instance to check the behaviour.

* ROP2vectors.txt : test vectors for the above file.

* testROP2.bat : MS-DOS batch file that compiles and
  runs the whole testbench. it is configured for
  Simili.

* ROP2vectors.out.txt : output of the testbench

       ############ Misc. : ############

* testbench_template.vhdl : a template if you want
  to write your own testbench with VHDL. the
  interpreter is better than ROP2_testbench.vhdl
  and can be customized at will.

* README.txt : this file

* COPYING.txt : a copy of the GPL for your
  collecting pleasure.


As always :
- if you have any question
- if you find a bug, a wrong detail
- if you experience a problem with the toolsuite
- if you enhance/modify/change the files
 -> please contact us so we can take the remarks
    into account in the next distribution.

have fun,
YG
