(C) Yann Guidon 2001 (whygee@f-cpu.org) | slide 16 / 18
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The future of the FC0

- Addition of new execution units : LNS Add/Sub/Conversion, IEEE floating point units, Popcount/ECC ...
- Addition of other memory interfaces, ie DDR SDRAM
- Extension to 2-issue then 4-issue (5r3w then 2*5r3w)
- Coding constraint for a superscalar F-CPU :
  - 2-issue : 64/(2*3)= 10 instructions without dependency
  - 3-issue : 64/(3*3)= 7 ...
  - 4-issue : 64/(3*4)= 5 <-- current limit of the FC0