(C) Yann Guidon 2001 (whygee@f-cpu.org) | slide 12 / 18
"Verbatim copying and distribution of this entire article is permitted in any medium, provided this notice is preserved."

Connexion of the address bus

- If there is a TLB miss, the pointer register is marked as invalid and a future use of this register as pointer will trigger a trap at the decode stage.
- The address output by the TLB is compared to the address tags of the Fetcher, the L/SU, the internal Icache and Dcache.
- If there is a cache or buffer hit
  - the register is marked as valid
  - the data is brought to the LSU or the Fetcher (depending on the access type) if the data is not available in the required buffer.